Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. - Shing-Wu Tung; Jing-Yang Jou (Asian Test Symposium, 1998)

A Logical Fault Model for Library Coherence Checking. - Shing-Wu Tung; Jing-Yang Jou (J. Inf. Sci. Eng., 1998)

An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (Asian Test Symposium, 2001)

On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (HLDVT, 2001)

An AVPG for SOC design verification with port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ISCAS (5), 2001)

ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. - Chih-Yuan Chen; Shing-Wu Tung (ISQED, 2001)

On automatic-verification pattern generation for SoC withport-order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An automatic interconnection rectification technique for SoC design integration. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ASP-DAC, 2003)

SoC design integration by using automatic interconnection rectification. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (ISCAS (4), 2003)

Automatic interconnection rectification for SoC design verification based on the port order fault model. - Chun-Yao Wang; Shing-Wu Tung; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology. - Jen-Chieh Yeh; Kung-Ming Ji; Shing-Wu Tung; Shau-Yin Tseng (HPCC, 2011)

Low power design and dynamic power management system for VLIW DSP subsystem. - Hsien-Ching Hsieh; Shui-An Wen; Che-Yu Liao; Huang-Lun Lin; Po-Han Huang; Shing-Wu Tung (ISPACS, 2011)

Low power and high performance 3-D multimedia platform. - Po-Han Huang; Chi-Hung Lin; Hsien-Ching Hsieh; Huang-Lun Lin; Shing-Wu Tung (Hot Chips Symposium, 2012)

A power management technology for mobile embedded system. - Shui-An Wen; Chun-Chin Chen; Shing-Wu Tung (VLSI-DAT, 2012)

A 42.5µW/MHz ultra-low power 32-bit microcontroller - SPARK. - Wei-Xiang Tang; Shui-An Wen; Shing-Wu Tung; Keng-Yu Lin; Chun-Chih Chen; Ching-Lung Su (ICICS, 2013)

A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. - Hsien-Ching Hsieh; Shr-Je Lin; Chun-Nan Liu; Jen-Chieh Yeh; Shing-Wu Tung; Ding-Ming Kwai (VLSI-DAT, 2013)