A 3.3-V 12-ns 16-Mb CMOS SRAM. - Hiroyuki Goto; Hiroaki Ohkubo; Kenji Kondou; Masayoshi Ohkawa; Hitoshi Mitani; Shinichi Horiba; Masakazu Soeda; Fumihiko Hayashi; Yutaro Hachiya; Toshiyuki Shimizu; Manabu Ando; Zensuke Matsuda (IEEE J. Solid State Circuits, 1992)

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. - Yasuhiro Takai; Mamoru Fujita; Kyoichi Nagata; Satoshi Isa; Shigeyuki Nakazawa; Atsunori Hirobe; Hiroaki Ohkubo; Masato Sakao; Shinichi Horiba; Tadashi Fukase; Yoshihiro Takaishi; Makoto Matsuo; et al. (IEEE J. Solid State Circuits, 2000)