0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. - Toshikazu Suzuki; Shinichi Moriwaki; Atsushi Kawasumi; Shinji Miyano; Hirofumi Shinohara (ESSCIRC, 2010)

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme. - Atsushi Kawasumi; Toshikazu Suzuki; Shinichi Moriwaki; Shinji Miyano (A-SSCC, 2011)

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. - Shinichi Moriwaki; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Shinji Miyano (CICC, 2011)

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. - Yasue Yamamoto; Atsushi Kawasumi; Shinichi Moriwaki; Toshikazu Suzuki; Shinji Miyano; Hirofumi Shinohara (ESSCIRC, 2012)

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. - Shusuke Yoshimoto; Masaharu Terada; Youhei Umeki; Shunsuke Okumura; Atsushi Kawasumi; Toshikazu Suzuki; Shinichi Moriwaki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2012)

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. - Shinichi Moriwaki; Yasuhiro Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Shinji Miyano; Takayasu Sakurai; Hirofumi Shinohara (VLSIC, 2012)

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. - Shinji Miyano; Shinichi Moriwaki; Yasue Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2013)