LORES - Logic Reorganization System. - Shunichiro Nakamura; Shinichi Murai; Chiyoji Tanaka; Masayuki Terai; Hideo Fujiwara; Kozo Kinoshita (DAC, 1978)

A hierarchical placement procedure with a simple blocking scheme. - Shinichi Murai; Hiroo Tsuji; Morio Kakinuma; Kazumichi Sakaguchi; Chiyoji Tanaka (DAC, 1979)

An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2. - Chiyoji Tanaka; Shinichi Murai; Shunichiro Nakamura; Takuji Ogihara; Masayuki Terai; Kozo Kinoshita (DAC, 1981)

An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3. - Chiyoji Tanaka; Shinichi Murai; Hiroo Tsuji; Toshihiko Yahara; Kaoru Okazaki; Masayuki Terai; Reiji Katoh; Mikio Tachibana (DAC, 1981)

Test generation for scan design circuits with tri-state modules and bidirectional terminals. - Takuji Ogihara; Shinichi Murai; Yuzo Takamatsu; Kozo Kinoshita; Hideo Fujiwara (DAC, 1983)

PATEGE: an automatic DC parametric test generation system for series gated ECL circuits. - Takuji Ogihara; Shuichi Saruyama; Shinichi Murai (DAC, 1985)

LORES-2: A Logic Reorganization System. - Kiyoshi Enomoto; Shunichiro Nakamura; Takuji Ogihara; Shinichi Murai (IEEE Des. Test, 1985)

ASTA: LSI Design Management System. - Takuji Ogihara; Hiromi Toyoshima; Shinichi Murai (DAC, 1987)

Test generation for sequential circuits using individual initial value propagation. - Takuji Ogihara; Shuichi Saruyama; Shinichi Murai (ICCAD, 1988)

MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits. - Takuji Ogihara; K. Muroi; Genichi Yonemori; Shinichi Murai (DAC, 1989)

Rule-based testability rule check program. - Yasushi Koseko; C. Hiramine; Takuji Ogihara; Shinichi Murai (ICCD, 1990)

Tri-state bus conflict checking method for ATPG using BDD. - Yasushi Koseko; Takuji Ogihara; Shinichi Murai (ICCAD, 1993)