SH3: high code density, low power. - Atsushi Hasegawa; Ikuya Kawasaki; Kouji Yamada; Shinichi Yoshioka; Shumpei Kawasaki; Prasenjit Biswas (IEEE Micro, 1995)

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. - Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatsu; Shinichi Yoshioka; Kojiro Suzuki; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakurnu; et al. (IEEE J. Solid State Circuits, 1996)

SH-mobile - low power application processor for cellular [3G cellular phones]. - Shoichi Kamae; Takahiro Irita; Akifumi Tsukimori; Saneaki Tarnaki; Toshihiro Hattori; Shinichi Yoshioka (ISCAS (5), 2005)

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. - Makoto Ishikawa; Tatsuya Kamei; Yuki Kondo; Masanao Yamaoka; Yasuhisa Shimazaki; Motokazu Ozawa; Saneaki Tamaki; Mikio Furuyama; Tadashi Hoshi; Fumio Arakawa; Osamu Nishii; Kenji Hirose; et al. (IEICE Trans. Electron., 2005)

Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

SH-MobileG1: A single-chip application and dual-mode baseband processor. - Masayuki Ito; Takahiro Irita; Eiji Yamamoto; Kunihiko Nishiyama; Takao Koike; Yoshihiko Tsuchihashi; Hiroyuki Asano; Hiroshi Yagi; Saneaki Tamaki; Ken Tatezawa; Toshihiro Hattori; Shinichi Yoshioka; et al. (Hot Chips Symposium, 2006)

A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (ISSCC, 2006)

Development of processor cores for digital consumer appliances. - Fumio Arakawa; Tetsuya Yamada; Takashi Okada; Makoto Ishikawa; Yuki Kondo; Motokazu Ozawa; Tomoyuki Kodama; Osamu Nishii; Toshihiro Hattori; Tatsuya Kamei; Junichi Nishimoto; Shinichi Yoshioka (Syst. Comput. Jpn., 2006)

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS. - Masayuki Ito; Toshihiro Hattori; Takahiro Irita; Ken Tatezawa; Fumihito Tanaka; Kenji Hirose; Shinichi Yoshioka; Koji Ohno; Reiko Tsuchihashi; Minoru Sakata; Masayuki Yamamoto; Yuji Aral (ISSCC, 2007)

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. - Masao Naruse; Tatsuya Kamei; Toshihiro Hattori; Takahiro Irita; Kenichi Nitta; Takao Koike; Shinichi Yoshioka; Koji Ohno; Masahito Saigusa; Minoru Sakata; Yukio Kodama; Yuji Arai; et al. (ISSCC, 2008)

A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. - Tatsuya Kamei; Tetsuhiro Yamada; Takao Koike; Masayuki Ito; Takahiro Irita; Kenichi Nitta; Toshihiro Hattori; Shinichi Yoshioka (ASP-DAC, 2009)

A 342mW mobile application processor with full-HD multi-standard video codec. - Kenichi Iwata; Takahiro Irita; Seiji Mochizuki; Hiroshi Ueda; Masakazu Ehama; Motoki Kimura; Jun Takemura; Keiji Matsumoto; Eiji Yamamoto; Tadashi Teranuma; Katsuji Takakubo; Hiromi Watanabe; et al. (ISSCC, 2009)

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. - Masayuki Ito; Kenichi Nitta; Koji Ohno; Masahito Saigusa; Masaki Nishida; Shinichi Yoshioka; Takahiro Irita; Takao Koike; Tatsuya Kamei; Teruyoshi Komuro; Toshihiro Hattori; Yasuhiro Arai; et al. (IEEE J. Solid State Circuits, 2009)

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. - Kenichi Iwata; Takahiro Irita; Seiji Mochizuki; Hiroshi Ueda; Masakazu Ehama; Motoki Kimura; Jun Takemura; Keiji Matsumoto; Eiji Yamamoto; Tadashi Teranuma; Katsuji Takakubo; Hiromi Watanabe; et al. (IEEE J. Solid State Circuits, 2010)