Hardware Structure of a One-Chip Data Driven Processor: Q-p. - Katsuhiko Asada; Hiroaki Terada; Satoshi Matsumoto; Souichi Miyata; Hajime Asano; Hiroki Miura; Masahisa Shimizu; Shinji Komori; Takeshi Fukuhara; Kenji Shima (ICPP, 1987)

An elastic pipeline mechanism by self-timed circuits. - Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Katsuhiko Asada; Hiroaki Terada (IEEE J. Solid State Circuits, 1988)

The data-driven microprocessor. - Shinji Komori; Kenji Shima; Souichi Miyata; Toshiya Okamoto; Hiroaki Terada (IEEE Micro, 1989)

VLSI implementation of a variable-length pipeline scheme for data-driven processors. - Tetsuo Yamasaki; Kenji Shima; Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme. - Shinji Komori; Hidehiro Takata; Todhixuki Tamura; Fumixsdu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Hiroaki Nishikawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)

A 100-mega-access per second matching memory for a data-driven microprocessor. - Hidehiro Takata; Shinji Komori; Toshiyuki Tamura; Fumiyasu Asai; Hisakazu Sato; Takio Ohno; Takeshi Tokuda; Hiroki Nishikawa; Hirofumi Terada (IEEE J. Solid State Circuits, 1990)

A Data-Driven Architecture for Distributed Parallel Processing. - Toshiyuki Tamura; Shinji Komori; Fumiyasu Asai; Hirono Tsubota; Hisakazu Sato; Hidehiro Takata; Yoshihiro Seguchi; Takeshi Tokuda; Hiroaki Terada (ICCD, 1991)

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. - Narumi Sakashita; Fumihiro Okuda; Ken'ichi Shimomura; Hiroki Shimano; Mitsuhiro Hamada; Tetsuo Tada; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; Haruhiko Abe (ITC, 1996)

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. - Narumi Sakashita; Yasuhiko Nitta; Ken'ichi Shimomura; Fumihiro Okuda; Hiroki Shimano; Satoshi Yamakawa; Masaki Tsukude; Kazutami Arimoto; Shinji Baba; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; et al. (IEEE J. Solid State Circuits, 1996)

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. - Ken'ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Fumihiro Okuda; Toshiyuki Oashi; Yasuo Yamaguchi; Takahisa Eimori; Masahide Inuishi; Kazutami Arimoto; Shigeto Maegawa; Yasuo Inoue; Shinji Komori; et al. (IEEE J. Solid State Circuits, 1997)