Single board video codec for ISDN visual telephone. - Tetsuo Tajiri; Yutaka Suzuki; Shinji Nishimura; Hiroshi Yoshimura (ICASSP, 1991)

RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection. - Shinji Nishimura; Katsuyoshi Harasawa; N. Matsudaira; Shigeto Akutsu; Tomohiro Kudoh; Hiroaki Nishi; Hideharu Amano (New Gener. Comput., 2000)

RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing. - Shinji Nishimura; Tomohiro Kudoh; Hiroaki Nishi; Junji Yamamoto; Ryuichiro Ueno; Katsuyoshi Harasawa; Shuji Fukuda; Yasutaka Shikichi; Shigeto Akutsu; Koji Tasho; Hideharu Amano (Hot Interconnects, 2001)

A 100-Gb-Ethernet subsystem for next-generation metro-area network. - Hidehiro Toyoda; Shinji Nishimura; Michitaka Okuno; Ryouji Yamaoka; Hiroaki Nishi (ICC, 2005)

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic. - Michitaka Okuno; Shinji Nishimura; Shinichi Ishida; Hiroaki Nishi (IEICE Trans. Electron., 2006)

100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet. - Hidehiro Toyoda; Shinji Nishimura; Michitaka Okuno; Kouji Fukuda; Kouji Nakahara; Hiroaki Nishi (IEICE Trans. Commun., 2006)

Basic Simulation Result of Inter System Handover for Cognitive Radio. - Takashi Ishikawa; Seishi Hanaoka; Mikio Kataoka; Masashi Yano; Shinji Nishimura (FGCN (2), 2007)

A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications. - Hidehiro Toyoda; Shinji Nishimura; Michitaka Okuno; Matsuaki Terada (IEICE Trans. Electron., 2007)

A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet. - Hidehiro Toyoda; Michitaka Okuno; Shinji Nishimura; Matsuaki Terada (ICC, 2008)

Technologies to Save Power for Carrier Class Routers and Switches. - Masaki Yamada; Takeki Yazaki; Shinji Nishimura; Naoya Ikeda (SAINT, 2008)

A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. - Takashi Takemoto; Fumio Yuki; Hiroki Yamashita; Shinji Tsuji; Tatsuya Saito; Shinji Nishimura (CICC, 2010)

100GbE PHY and MAC layer implementations. - Hidehiro Toyoda; Goichi Ono; Shinji Nishimura (IEEE Commun. Mag., 2010)

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (ISSCC, 2011)

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (IEEE J. Solid State Circuits, 2011)

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. - Takashi Takemoto; Hiroki Yamashita; Takehito Kamimura; Fumio Yuki; Noboru Masuda; Hidehiro Toyoda; Norio Chujo; Kenji Kogo; Yong Lee; Shinji Tsuji; Shinji Nishimura (VLSIC, 2012)

A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology. - Masashi Kono; Akihiro Kambe; Hidehiro Toyoda; Shinji Nishimura (IEICE Trans. Commun., 2012)

Compact and power-efficient 100-Gbps CMOS-based transceiver. - Takashi Takemoto; Hiroki Yamashita; Fumio Yuki; Shinji Tsuji; Yong Lee; Koichiro Adachi; Kazunori Shinoda; Yasunobu Matsuoka; Toshiki Sugawara; Shinji Nishimura; Norio Chujo; Masaaki Nido; et al. (OFC/NFOEC, 2013)

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. - Takashi Takemoto; Hiroki Yamashita; Fumio Yuki; Noboru Masuda; Hidehiro Toyoda; Norio Chujo; Yong Lee; Shinji Tsuji; Shinji Nishimura (IEEE J. Solid State Circuits, 2014)