Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. - Koichi Takeda 001; Toshio Saito; Shinobu Asayama; Yoshiharu Aimoto; Hiroyuki Kobatake; Shinya Ito; Toshifumi Takahashi; Masahiro Nomura; Kiyoshi Takeuchi; Yoshihiro Hayashi (IEEE J. Solid State Circuits, 2011)

40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues. - Yoshisato Yokoyama; Yuichiro Ishii; Koji Tanaka; Tatsuya Fukuda; Yoshiki Tsujihashi; Atsushi Miyanishi; Shinobu Asayama; Keiichi Maekawa; Kazutoshi Shiba; Koji Nii (A-SSCC, 2014)

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU. - Yoshisato Yokoyama; Yuichiro Ishii; Hidemitsu Kojima; Atsushi Miyanishi; Yoshiki Tsujihashi; Shinobu Asayama; Kazutoshi Shiba; Koji Tanaka; Tatsuya Fukuda; Koji Nii; Kazumasa Yanagisawa (ISQED, 2014)