A macro analysis of soft errors in static RAMs. - Yasunobu Nakase; Kenji Anami; Tohru Shiomi; Atsushi Ohba; Shinpei Kayano (IEEE J. Solid State Circuits, 1988)

A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. - Yasunobu Nakase; Kakutaro Suda; Koichiro Mashiko; Tatsuhiko Ikeda; Shinpei Kayano (IEEE J. Solid State Circuits, 1991)

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture. - Yutaka Arima; Koichiro Mashiko; Keisuke Okada; Tsuyoshi Yamada; Atsushi Maeda; Hiromi Notani; Harufusa Kondoh; Shinpei Kayano (IEEE J. Solid State Circuits, 1991)

A high-density data-path generator with stretchable cells. - Yoshiki Tsujihashi; Hisashi Matsumoto; Hidekatsu Nishimaki; Atsushi Miyanishi; Hiroomi Nakao; Osamu Kitada; Shuhei Iwade; Shinpei Kayano; Masayoshi Sakao (IEEE J. Solid State Circuits, 1994)

A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates. - Koji Nii; Hideshi Maeno; Tokuya Osawa; Shuhei Iwade; Shinpei Kayano; Hiroshi Shibata (IEEE J. Solid State Circuits, 1995)