Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. - Shintaro Harada; Xu Bai; Michitaka Kameyama; Yoshichika Fujioka (ISMVL, 2014)

Neural Machine Translation with Synchronous Latent Phrase Structure. - Shintaro Harada; Taro Watanabe (ACL (student), 2021)