A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. - Koh Johguchi; Yuya Mukuda; Shinya Izumi; Hans Jürgen Mattausch; Tetsushi Koide (ESSCIRC, 2007)

Measurement-Based Ring Oscillator Variation Analysis. - Koh Johguchi; Akihiro Kaya; Shinya Izumi; Hans Jürgen Mattausch; Tetsushi Koide; Norio Sadachika (IEEE Des. Test Comput., 2010)