Smart Core System for Dependable Many-Core Processor with Multifunction Routers. - Shinya Takamaeda; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (ICNC, 2010)

An FPGA-based scalable simulation accelerator for tile architectures. - Shinya Takamaeda-Yamazaki; Ryosuke Sasakawa; Yoshito Sakaguchi; Kenji Kise (SIGARCH Comput. Archit. News, 2011)

ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. - Shinya Takamaeda-Yamazaki; Shintaro Sano; Yoshito Sakaguchi; Naoki Fujieda; Kenji Kise (ARC, 2012)

Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations. - Ryohei Kobayashi 001; Shinya Takamaeda-Yamazaki; Kenji Kise (ICNC, 2012)

Ultrasmall: The smallest MIPS soft processor. - Hiroshi Nakatsuka; Yuichiro Tanaka; Thiem Van Chu; Shinya Takamaeda-Yamazaki; Kenji Kise (FPL, 2014)

flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. - Shinya Takamaeda-Yamazaki; Kenji Kise (FPL, 2014)

A framework for efficient rapid prototyping by virtually enlarging FPGA resources. - Shinya Takamaeda-Yamazaki; Kenji Kise (ReConFig, 2014)

Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. - Shinya Takamaeda-Yamazaki (ARC, 2015)

A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations. - Shohei Takeuchi; Yuttakon Yuttakonkit; Shinya Takamaeda-Yamazaki; Yasuhiko Nakashima (CANDAR, 2015)

A CGRA-Based Approach for Accelerating Convolutional Neural Networks. - Masakazu Tanomoto; Shinya Takamaeda-Yamazaki; Jun Yao 001; Yasuhiko Nakashima (MCSoC, 2015)

Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. - Yoshikazu Inagaki; Shinya Takamaeda-Yamazaki; Jun Yao 001; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2015)

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs. - Shinya Takamaeda-Yamazaki; Hiroshi Nakatsuka; Yuichiro Tanaka; Kenji Kise (IEICE Trans. Inf. Syst., 2015)

Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs. - Keisuke Fujimoto; Shinya Takamaeda-Yamazaki; Yasuhiko Nakashima (CANDAR, 2016)

CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. - Hiromasa Kato; Satoshi Shimaya; Keisuke Fujimoto; Tomoya Kameda; Thi Hong Tran; Shinya Takamaeda-Yamazaki; Yasuhiko Nakashima (CANDAR, 2016)

CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing. - Hoang Gia Vu; Supasit Kajkamhaeng; Shinya Takamaeda-Yamazaki; Yasuhiko Nakashima (CANDAR, 2016)

Performance Optimization of Light-Field Applications on GPU. - Yuttakon Yuttakonkit; Shinya Takamaeda-Yamazaki; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2016)

Accelerating deep learning by binarized hardware. - Shinya Takamaeda-Yamazaki; Kodai Ueyoshi; Kota Ando; Ryota Uematsu; Kazutoshi Hirose; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (APSIPA, 2017)

CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. - Hoang Gia Vu; Shinya Takamaeda-Yamazaki; Takashi Nakada; Yasuhiko Nakashima (FCCM, 2017)

FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. - Aoi Tanibata; Alexandre Schmid; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Masato Motomura; Tetsuya Asai (FPL, 2017)

A Time-Division Multiplexing Ising Machine on FPGAs. - Kasho Yamamoto; Weiqiang Huang; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (HEART, 2017)

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. - Kazutoshi Hirose; Ryota Uematsu; Kota Ando; Kentaro Orimo; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (CANDAR, 2017)

In-memory area-efficient signal streaming processor design for binary neural networks. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Kota Ando; Kodai Ueyoshi; Kazutoshi Hirose; Kentaro Orimo; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (MWSCAS, 2017)

Quantization Error-Based Regularization in Neural Networks. - Kazutoshi Hirose; Kota Ando; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (SGAI Conf., 2017)

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (FPT, 2018)

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. - Takeshi Shimada; Masayuki Ikebe; Prasoon Ambalathankandy; Shinya Takamaeda-Yamazaki; Masato Motomura; Tetsuya Asai (ICASSP, 2018)

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Junichiro Kadomoto; Tomoki Miyata; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (ISSCC, 2018)

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. - Takumi Kudo; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Ryota Uematsu; Yuka Oba; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (MCSoC, 2018)

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. - Prasoon Ambalathankandy; Takeshi Shimada; Shinya Takamaeda; Masato Motomura; Tetsuya Asai; Masayuki Ikebe (VCIP, 2018)

Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. - Aoi Tanibata; Alexandre Schmid; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Masato Motomura; Tetsuya Asai (Complex., 2018)

A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. - Hoang Gia Vu; Shinya Takamaeda-Yamazaki; Takashi Nakada; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2018)

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. - Kota Ando; Kodai Ueyoshi; Kentaro Orimo; Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2018)

Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. - Prasoon Ambalathankandy; Shinya Takamaeda; Masato Motomura; Tetsuya Asai; Masayuki Ikebe; Hotaka Kusano (Microprocess. Microsystems, 2018)

DeltaNet: Differential Binary Neural Network. - Yuka Oba; Kota Ando; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (ASAP, 2019)

Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. - Prasoon Ambalathankandy; Yafei Ou; Jyotsna Kochiyil; Shinya Takamaeda; Masato Motomura; Tetsuya Asai; Masayuki Ikebe (DICTA, 2019)

A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. - Yuki Hirayama; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (CANDAR, 2019)

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEICE Trans. Inf. Syst., 2019)

FPGA-Based Annealing Processor with Time-Division Multiplexing. - Kasho Yamamoto; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (IEICE Trans. Inf. Syst., 2019)

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2019)

Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. - Taiga Ikeda; Kento Sakurada; Atsuyoshi Nakamura; Masato Motomura; Shinya Takamaeda-Yamazaki (ARC, 2020)

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2020)

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. - Kasho Yamamoto; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (ISSCC, 2020)

A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. - Yuki Hirayama; Tetsuya Asai; Masato Motomura; Shinya Takamaeda (Int. J. Netw. Comput., 2020)

An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. - Prasoon Ambalathankandy; Masayuki Ikebe; Takayuki Yoshida; Takeshi Shimada; Shinya Takamaeda; Masato Motomura; Tetsuya Asai (IEEE Trans. Circuits Syst. Video Technol., 2020)

ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design. - Yoshiki Fujiwara; Shinya Takamaeda-Yamazaki (ASAP, 2021)

An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. - Nobuho Hashimoto; Shinya Takamaeda-Yamazaki (FPL, 2021)

Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. - Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Jaehoon Yu; Masato Motomura (IEEE Access, 2021)

Foreword. - Shinya Takamaeda (IEICE Trans. Inf. Syst., 2021)

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. - Kasho Yamamoto; Kazushi Kawamura; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEEE J. Solid State Circuits, 2021)

A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. - Nobuho Hashimoto; Shinya Takamaeda-Yamazaki (FPT, 2022)

Model-based Federated Reinforcement Distillation. - Sefutsu Ryu; Shinya Takamaeda-Yamazaki (GLOBECOM, 2022)

Accelerating Decision Tree Ensemble with Guided Branch Approximation. - Keisuke Kamahori; Shinya Takamaeda-Yamazaki (HEART, 2022)

Multi-Input Adaptive Activation Function for Binary Neural Networks. - Peiqi Zhang; Shinya Takamaeda-Yamazaki (CANDARW, 2022)

MP-GELU Bayesian Neural Networks: Moment Propagation by GELU Nonlinearity. - Yuki Hirayama; Shinya Takamaeda-Yamazaki (CoRR, 2022)

Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. - Yafei Ou; Prasoon Ambalathankandy; Shinya Takamaeda; Masato Motomura; Tetsuya Asai; Masayuki Ikebe (IEEE Trans. Circuits Syst. Video Technol., 2022)

High-Level Synthesis of Memory Systems for Decoupled Data Orchestration. - Masayuki Usui; Shinya Takamaeda-Yamazaki (ARC, 2023)

SPinS-FL: Communication-Efficient Federated Subnetwork Learning. - Masayoshi Tsutsui; Shinya Takamaeda-Yamazaki (CCNC, 2023)

Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory. - Tatsuya Kubo; Shinya Takamaeda-Yamazaki (COOL CHIPS, 2023)

GeMP-BNN: High-Performance Sampling-Free Bayesian Neural Network Accelerator with Gaussian Error Moment Propagation. - Yuki Hirayama; Kengo Suga; Shinya Takamaeda-Yamazaki (MCSoC, 2023)

MAO: Memory Architecture Obfuscation. - Sun Tanaka; Shinya Takamaeda-Yamazaki (MCSoC, 2023)

Poison Egg: Scrambling Federated Learning with Delayed Backdoor Attack. - Masayoshi Tsutsui; Tatsuya Kaneko; Shinya Takamaeda-Yamazaki (UbiSec, 2023)

HALO-CAT: A Hidden Network Processor with Activation-Localized CIM Architecture and Layer-Penetrative Tiling. - Yung-Chin Chen; Shimpei Ando; Daichi Fujiki; Shinya Takamaeda-Yamazaki; Kentaro Yoshioka (CoRR, 2023)

MITA: Multi-Input Adaptive Activation Function for Accurate Binary Neural Network Hardware. - Peiqi Zhang; Shinya Takamaeda-Yamazaki (IEICE Trans. Inf. Syst., 2023)

OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. - Yung-Chin Chen; Shimpei Ando; Daichi Fujiki; Shinya Takamaeda-Yamazaki; Kentaro Yoshioka (ASPDAC, 2024)

FS-Boost: Communication-Efficient Federated Subtree-Based Gradient Boosting Decision Trees. - Kotaro Shimamura; Shinya Takamaeda-Yamazaki (CCNC, 2024)

PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation. - Wenlun Zhang; Shimpei Ando; Yung-Chin Chen; Satomi Miyagi; Shinya Takamaeda-Yamazaki; Kentaro Yoshioka (ICCAD, 2024)

Federated Learning with Relative Fairness. - Shogo Nakakita; Tatsuya Kaneko; Shinya Takamaeda-Yamazaki; Masaaki Imaizumi (CoRR, 2024)

Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems. - Tatsuya Kubo; Shinya Takamaeda-Yamazaki (IEEE Micro, 2024)

Accelerating Elliptic Curve Point Additions on Versal AI Engine for Multi-Scalar Multiplication. - Ayumi Ohno; Kotaro Shimamura; Shinya Takamaeda-Yamazaki (COOL CHIPS, 2025)

RustSFQ: A Domain-Specific Language for SFQ Circuit Design. - Mebuki Oishi; Sun Tanaka; Shinya Takamaeda-Yamazaki (COOL CHIPS, 2025)

Exploring the Versal AI Engine for 3D Gaussian Splatting. - Kotaro Shimamura; Ayumi Ohno; Shinya Takamaeda-Yamazaki (COOL CHIPS, 2025)

PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM. - Tatsuya Kubo; Daichi Tokuda; Lei Qu; Ting Cao; Shinya Takamaeda-Yamazaki (IEEE Comput. Archit. Lett., 2025)

MVDRAM: Enabling GeMV Execution in Unmodified DRAM for Low-Bit LLM Acceleration. - Tatsuya Kubo; Daichi Tokuda; Tomoya Nagatani; Masayuki Usui; Lei Qu; Ting Cao; Shinya Takamaeda-Yamazaki (CoRR, 2025)

Scalable Moment Propagation and Analysis of Variational Distributions for Practical Bayesian Deep Learning. - Yuki Hirayama; Shinya Takamaeda-Yamazaki (IEEE Trans. Neural Networks Learn. Syst., 2025)

Uncertainty in Machine Learning and Future Computers. - Shinya Takamaeda-Yamazaki (Computer, 2025)

PRIOT: Pruning-Based Integer-Only Transfer Learning for Embedded Systems. - Honoka Anada; Sefutsu Ryu; Masayuki Usui; Tatsuya Kaneko; Shinya Takamaeda-Yamazaki (IEEE Embed. Syst. Lett., 2025)

Measuring Participant Contributions in Decentralized Federated Learning. - Honoka Anada; Tatsuya Kaneko; Shinya Takamaeda-Yamazaki (CoRR, 2025)

DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination. - Daichi Tokuda; Shinya Takamaeda-Yamazaki (ACM Trans. Reconfigurable Technol. Syst., 2025)