A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS. - Chun-Yuan Cheng; Jinn-Shyan Wang; Pei-Yuan Chou; Shiou-Ching Chen; Chi-Tien Sun; Yuan-Hua Chu; Tzu-Yi Yang (A-SSCC, 2014)