Development of a CMOS Data Recovery PLL for DVD-ROMx14. - Shiro Dosho; Naoshi Yanagisawa; Seiji Watanabe; Takahiro Bokui; Kazuhiko Nishikawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process. - Shiro Dosho; Takashi Morie; Hirokuni Fujiyama (IEEE J. Solid State Circuits, 2002)

A background optimization method for PLL by measuring phase jitter performance. - Shiro Dosho; Naoshi Yanagisawa; Akira Matsuzawa (IEEE J. Solid State Circuits, 2005)

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution. - Shiro Dosho; Shiro Sakiyama; Noriaki Takeda; Yusuke Tokunaga; Takashi Morie (ISSCC, 2006)

A 0.03mm2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface. - Yusuke Tokunaga; Shiro Sakiyama; Shiro Dosho; Yasuyuki Doi; Makoto Hattori (ISSCC, 2006)

A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit. - Shiro Dosho; Takashi Morie; Koji Okamoto; Yuji Yamada; Kazuaki Sogawa (IEICE Trans. Electron., 2006)

An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter. - Shiro Dosho; Naoshi Yanagisawa; Kazuaki Sogawa; Yuji Yamada; Takashi Morie (IEICE Trans. Electron., 2007)

A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System. - Akinori Matsumoto; Shiro Sakiyama; Yusuke Tokunaga; Takashi Morie; Shiro Dosho (IEEE J. Solid State Circuits, 2008)

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. - Kazuo Matsukawa; Takashi Morie; Yusuke Tokunaga; Shiro Sakiyama; Yosuke Mitani; Masao Takayama; Takuji Miki; Akinori Matsumoto; Koji Obata; Shiro Dosho (ASP-DAC, 2009)

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage. - Yusuke Tokunaga; Shiro Sakiyama; Akinori Matsumoto; Shiro Dosho (ISSCC, 2009)

A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. - Tsuyoshi Ebuchi; Yoshihide Komatsu; Tatsuo Okamoto; Yukio Arima; Yuji Yamada; Kazuaki Sogawa; Kouji Okamoto; Takashi Morie; Takashi Hirata; Shiro Dosho; Takefumi Yoshikawa (IEEE J. Solid State Circuits, 2009)

A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver. - Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Koji Obata; Yusuke Tokunaga; Shiro Sakiyama; Shiro Dosho (CICC, 2010)

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator. - Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Koji Obata; Shiro Dosho; Akira Matsuzawa (IEEE J. Solid State Circuits, 2010)

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback. - Yusuke Tokunaga; Shiro Sakiyama; Akinori Matsumoto; Shiro Dosho (IEEE J. Solid State Circuits, 2010)

An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration. - Tsuyoshi Ebuchi; Yoshihide Komatsu; Masatomo Miura; Tomoko Chiba; Toru Iwata; Shiro Dosho; Takefumi Yoshikawa (IEEE J. Solid State Circuits, 2011)

A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method. - Kazuo Matsukawa; Koji Obata; Yosuke Mitani; Shiro Dosho (VLSIC, 2012)

Foreword. - Shiro Dosho (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Digital Calibration and Correction Methods for CMOS Analog-to-Digital Converters. - Shiro Dosho (IEICE Trans. Electron., 2012)

Continuous-Time Delta-Sigma Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey. - Shiro Dosho (IEICE Trans. Electron., 2012)

A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver. - Koji Obata; Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Yusuke Tokunaga; Shiro Sakiyama; Shiro Dosho (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. - Takuji Miki; Takashi Morie; Toshiaki Ozeki; Shiro Dosho (IEEE J. Solid State Circuits, 2012)

Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs. - Shinichiro Uemura; Yukio Hiraoka; Takayuki Kai; Shiro Dosho (IEEE J. Solid State Circuits, 2012)

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. - Takashi Morie; Takuji Miki; Kazuo Matsukawa; Yoji Bando; Takeshi Okumoto; Koji Obata; Shiro Sakiyama; Shiro Dosho (ISSCC, 2013)

A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells. - Masao Takayama; Shiro Dosho; Noriaki Takeda; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2013)

12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. - Noriyuki Miura; Shiro Dosho; Satoshi Takaya; Daisuke Fujimoto; Takuya Kiriyama; Hiroyuki Tezuka; Takuji Miki; Hiroto Yanagawa; Makoto Nagata (ISSCC, 2014)

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. - Takuji Miki; Takashi Morie; Kazuo Matsukawa; Yoji Bando; Takeshi Okumoto; Koji Obata; Shiro Sakiyama; Shiro Dosho (IEEE J. Solid State Circuits, 2015)

A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. - Noriyuki Miura; Shiro Dosho; Hiroyuki Tezuka; Takuji Miki; Daisuke Fujimoto; Takuya Kiriyama; Makoto Nagata (IEEE J. Solid State Circuits, 2015)

A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. - Takuji Miki; Noriyuki Miura; Kento Mizuta; Shiro Dosho; Makoto Nagata (ESSCIRC, 2016)

An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. - Sho Ikeda; Hiroyuki Ito; Akifumi Kasamatsu; Yosuke Ishikawa; Takayoshi Obara; Naoki Noguchi; Koji Kamisuki; Yao Jiyang; Shinsuke Hara; Ruibing Dong; Shiro Dosho; Noboru Ishihara; et al. (VLSI Circuits, 2016)

Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. - Yosuke Ishikawa; Sho Ikeda; Hiroyuki Ito; Akifumi Kasamatsu; Takayoshi Obara; Naoki Noguchi; Koji Kamisuki; Yao Jiyang; Shinsuke Hara; Ruibing Dong; Shiro Dosho; Noboru Ishihara; et al. (ASP-DAC, 2017)

A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. - Takuji Miki; Noriyuki Miura; Kento Mizuta; Shiro Dosho; Makoto Nagata (IEICE Trans. Electron., 2017)

A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique. - Sho Ikeda; Hiroyuki Ito; Akifumi Kasamatsu; Yosuke Ishikawa; Takayoshi Obara; Naoki Noguchi; Koji Kamisuki; Yao Jiyang; Shinsuke Hara; Ruibing Dong; Shiro Dosho; Noboru Ishihara; et al. (IEEE J. Solid State Circuits, 2017)

A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers. - Motohiro Takayasu; Shiro Dosho; Hiroyuki Ito; Daisuke Yamane; Toshifumi Konishi; Katsuyuki Machida; Noboru Ishihara; Kazuya Masu (IEICE Electron. Express, 2018)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Towards Digital Synthesis of Variable Q-Factor Direct-Conversion for Low-Power Edge Sensing. - Parthojit Chakraborty; Kazuki Maari; Jim Bartels; Alexandre Varieras; Aravind Tharayil Narayanan; Ludovico Minati; Shiro Dosho; Hiroyuki Ito (SENSORS, 2023)

A Compact 0.9uW Direct-Conversion Frequency Analyzer for Speech Recognition with Wide-Range Q-Controlable Bandpass Rectifier. - Shiro Dosho; Ludovico Minati; Kazuki Maari; Hiroyuki Ito (VLSI Technology and Circuits, 2023)

A neural network-based DPD coefficient determination for PA linearization in 5G and beyond-5G mmWave systems. - Aravind Tharayil Narayanan; Ludovico Minati; Aran Hagihara; Jun Kobayashi; Toshihiro Shimura; Yoichi Kawano; Parthojit Chakraborty; Jim Bartels; Korkut Kaan Tokgoz; Shiro Dosho; Toshihide Suzuki; Hiroyuki Ito (IEICE Electron. Express, 2024)

A Compact 0.9μ W Direct-Conversion Frequency Analyzer for Speech Recognition With Wide- Range Q-Controllable Bandpass Rectifier. - Shiro Dosho; Ludovico Minati; Kazuki Maari; Shungo Ohkubo; Hiroyuki Ito (IEEE Trans. Very Large Scale Integr. Syst., 2025)