A 209 K-transistor ECL gate array with RAM. - Hisayasu Sato; Takashi Nishimura; Makoto Tatsuki; Atsushi Ohba; Shiro Hine; Yoichi Kuramitsu (IEEE J. Solid State Circuits, 1989)

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture. - Toru Shiomi; Tomohisa Wada; Shigeki Ohbayashi; Atsushi Ohba; Hiroki Honda; Yoshiyuki Ishigaki; Shiro Hine; Kenji Anami; Kimio Suzuki; Tadashi Sumi (IEEE J. Solid State Circuits, 1993)