Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design. - Mikako Miyama; Shiro Kamohara; Mitsuru Hiraki; Kazunori Onozawa; Hisaaki Kunitomo (CICC, 1999)

Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters. - Mikako Miyama; Shiro Kamohara (ASP-DAC, 2000)

Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure. - Yuichi Hamamura; Kazunori Nemoto; Takaaki Kumazawa; Hisafumi Iwata; Kousuke Okuyama; Shiro Kamohara; Aritoshi Sugimoto (DFT, 2002)

Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. - Kenichi Osada; Naoki Kitai; Shiro Kamohara; Takayuki Kawahara (CICC, 2004)

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. - Akira Kotabe; Kenichi Osada; Naoki Kitai; Mio Fujioka; Shiro Kamohara; Masahiro Moniwa; Sadayuki Morita; Yoshikazu Saitoh (IEEE J. Solid State Circuits, 2005)

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node. - Hideaki Kurata; Kazuo Otsuga; Akira Kotabe; Shinya Kajiyama; Taro Osabe; Yoshitaka Sasago; Shunichi Narumi; Kenji Tokami; Shiro Kamohara; Osamu Tsuchiya (IEEE J. Solid State Circuits, 2007)

A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis. - Chizu Matsumoto; Yuichi Hamamura; Yoshiyuki Tsunoda; Hiroshi Uozaki; Isao Miyazaki; Shiro Kamohara; Yoshiyuki Kaneko; Kenji Kanamitsu (IEICE Trans. Electron., 2011)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. - Koichiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguchi; Hidekazu Oda; et al. (COOL Chips, 2014)

0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM. - Toshitsugu Sakamoto; Yukihide Tsuji; Munehiro Tada; Hideki Makiyama; Takumi Hasegawa; Yoshiki Yamamoto; Shinobu Okanishi; Keiichi Maekawa; Naoki Banno; Makoto Miyamura; Koichiro Okamoto; Noriyuki Iguchi; et al. (COOL Chips, 2015)

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process. - Duc-Hung Le; Nobuyuki Sugii; Shiro Kamohara; Xuan-Thuan Nguyen; Koichiro Ishibashi; Cong-Kha Pham (ICICDT, 2015)

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. - Koichiro Ishibashi; Nobuyuki Sugii; Shiro Kamohara; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham (IEICE Trans. Electron., 2015)

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM. - Toshitsugu Sakamoto; Yukihide Tsuji; Munehiro Tada; Hideki Makiyama; Takumi Hasegawa; Yoshiki Yamamoto; Shinobu Okanishi; Keiichi Maekawa; Naoki Banno; Makoto Miyamura; Koichiro Okamoto; Noriyuki Iguchi; et al. (IEEE Micro, 2015)

SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive. - Takumi Hasegawa; Yoshiki Yamamoto; Hideki Makiyama; Hiroki Shinkawata; Shiro Kamohara; Yasuo Yamaguchi (ICICDT, 2017)