An image signal multiprocessor on a single chip. - Masakatsu Maruyama; Hiroyuki Nakahira; Toshiyuki Araki; Shiro Sakiyama; Yoshitaka Kitao; Kunitoshi Aono; Haruyasu Yamada (IEEE J. Solid State Circuits, 1990)

Quantizer neuron model and neuroprocessor-named quantizer neuron chip. - Susumu Maruno; Toshiyuki Kohda; Hiroyuki Nakahira; Shiro Sakiyama; Masakatsu Maruyama (IEEE J. Sel. Areas Commun., 1994)

Mixed body bias techniques with fixed Vt and Ids generation circuits. - Masaya Sumita; Shiro Sakiyama; Masayoshi Kinoshita; Yuta Araki; Yuichiro Ikeda; Kohei Fukuoka (IEEE J. Solid State Circuits, 2005)

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution. - Shiro Dosho; Shiro Sakiyama; Noriaki Takeda; Yusuke Tokunaga; Takashi Morie (ISSCC, 2006)

A 0.03mm2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface. - Yusuke Tokunaga; Shiro Sakiyama; Shiro Dosho; Yasuyuki Doi; Makoto Hattori (ISSCC, 2006)

A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System. - Akinori Matsumoto; Shiro Sakiyama; Yusuke Tokunaga; Takashi Morie; Shiro Dosho (IEEE J. Solid State Circuits, 2008)

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. - Kazuo Matsukawa; Takashi Morie; Yusuke Tokunaga; Shiro Sakiyama; Yosuke Mitani; Masao Takayama; Takuji Miki; Akinori Matsumoto; Koji Obata; Shiro Dosho (ASP-DAC, 2009)

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage. - Yusuke Tokunaga; Shiro Sakiyama; Akinori Matsumoto; Shiro Dosho (ISSCC, 2009)

A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver. - Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Koji Obata; Yusuke Tokunaga; Shiro Sakiyama; Shiro Dosho (CICC, 2010)

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback. - Yusuke Tokunaga; Shiro Sakiyama; Akinori Matsumoto; Shiro Dosho (IEEE J. Solid State Circuits, 2010)

A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver. - Koji Obata; Kazuo Matsukawa; Yosuke Mitani; Masao Takayama; Yusuke Tokunaga; Shiro Sakiyama; Shiro Dosho (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. - Takashi Morie; Takuji Miki; Kazuo Matsukawa; Yoji Bando; Takeshi Okumoto; Koji Obata; Shiro Sakiyama; Shiro Dosho (ISSCC, 2013)

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. - Takuji Miki; Takashi Morie; Kazuo Matsukawa; Yoji Bando; Takeshi Okumoto; Koji Obata; Shiro Sakiyama; Shiro Dosho (IEEE J. Solid State Circuits, 2015)