Towards a Better Cache Utilization Using Controlled Cache Partitioning. - Prateek D. Halwe; Shirshendu Das; Hemangee K. Kapoor (DASC, 2013)

Dynamic Associativity Management Using Fellow Sets. - Shirshendu Das; Hemangee K. Kapoor (ISED, 2013)

Random-LRU: A Replacement Policy for Chip Multiprocessors. - Shirshendu Das; Nagaraju Polavarapu; Prateek D. Halwe; Hemangee K. Kapoor (VDAT, 2013)

A formal framework for interfacing mixed-timing systems. - Shirshendu Das; Parasara Sridhar Duggirala; Hemangee K. Kapoor (Integr., 2013)

Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors. - Hemangee K. Kapoor; Praveen Kanakala; Malti Verma; Shirshendu Das (J. Supercomput., 2013)

RT-DVS for Power Optimization in Multiprocessor Real-Time Systems. - B. Venkateswarlu Naik; Shirshendu Das; Hemangee K. Kapoor (ICIT, 2014)

An Approach for Multicast Routing in Networks-on-Chip. - M. Lakshmi Prasad; Shirshendu Das; Hemangee K. Kapoor (ICIT, 2014)

Victim retention for reducing cache misses in tiled chip multiprocessors. - Shirshendu Das; Hemangee K. Kapoor (Microprocess. Microsystems, 2014)

Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. - Shounak Chakraborty 001; Shirshendu Das; Hemangee K. Kapoor (IPDPS Workshops, 2015)

Dynamic associativity management using utility based way-sharing. - Shirshendu Das; Hemangee K. Kapoor (SAC, 2015)

Static energy reduction by performance linked cache capacity management in tiled CMPs. - Hemangee K. Kapoor; Shirshendu Das; Shounak Chakraborty 001 (SAC, 2015)

Power aware cache miss reduction by energy efficient victim retention. - Shounak Chakraborty 001; Shirshendu Das; Hemangee K. Kapoor (VDAT, 2015)

An efficient searching mechanism for dynamic NUCA in chip multiprocessors. - Kartheek Vanapalli; Hemangee K. Kapoor; Shirshendu Das (VDAT, 2015)

Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. - Shirshendu Das; Hemangee K. Kapoor (VLSID, 2015)

Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. - Shounak Chakraborty 001; Shirshendu Das; Hemangee K. Kapoor (SAC, 2016)

Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs. - Shirshendu Das; Hemangee K. Kapoor (SAC, 2016)

Tag only storage for capacity optimised last level cache in chip multiprocessors. - Surajit Das; Shirshendu Das; Hemangee K. Kapoor (VDAT, 2016)

Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. - Shirshendu Das; Hemangee K. Kapoor (VLSID, 2016)

A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture. - Shirshendu Das; Hemangee K. Kapoor (ACM Trans. Design Autom. Electr. Syst., 2016)

Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. - Shirshendu Das; Hemangee K. Kapoor (ISVLSI, 2017)

Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets. - Shirshendu Das; Hemangee K. Kapoor (IEEE Trans. Parallel Distributed Syst., 2017)

Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. - Alankar V. Umdekar; Arijit Nath; Shirshendu Das; Hemangee K. Kapoor (VLSID, 2018)

State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency. - Kaustav Goswami 002; Hemanta Kumar Mondal; Shirshendu Das; Dip Sankar Banerjee (ISQED, 2019)

Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. - Dipika Deb; John Jose; Shirshendu Das; Hemangee K. Kapoor (J. Parallel Distributed Comput., 2019)

Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache. - Anurag Agarwal; Jaspinder Kaur; Shirshendu Das (DATE, 2021)

A Fairness Conscious Cache Replacement Policy for Last Level Cache. - Kousik Kumar Dutta; Prathamesh Nitin Tanksale; Shirshendu Das (DATE, 2021)

Towards Row Sensitive DRAM Refresh through Retention Awareness. - Tanmay Goel; Divyansh Maura; Kaustav Goswami 002; Shirshendu Das; Dip Sankar Banerjee (ISQED, 2021)

MAPCP: Memory Access Pattern Classifying Prefetcher. - Manaal Mukhtar Jamadar; Jaspinder Kaur; Shirshendu Das (MEMSYS, 2021)

Efficient On-chip Communication for Neuromorphic Systems. - Shobhit Kumar; Shirshendu Das; Manaal Mukhtar Jamadar; Jaspinder Kaur (SmartWorld/SCALCOM/UIC/ATC/IOP/SCI, 2021)

A Survey on Cache Timing Channel Attacks for Multicore Processors. - Jaspinder Kaur; Shirshendu Das (J. Hardw. Syst. Secur., 2021)

Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors. - Bindu Agarwalla; Shirshendu Das; Nilkanta Sahu (J. Syst. Archit., 2021)

Towards Enhanced System Efficiency while Mitigating Row Hammer. - Kaustav Goswami 002; Dip Sankar Banerjee; Shirshendu Das (ACM Trans. Archit. Code Optim., 2021)

PV-aware Replacement Policy for Two-level Shared Cache. - Bindu Agarwalla; Nilkanta Sahu; Shirshendu Das (iSES, 2022)

A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices. - Kaustav Goswami 002; Shirshendu Das; Sagar Satapathy; Dip Sankar Banerjee (MEMSYS, 2022)

Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly. - Samiksha Verma; Shirshendu Das; Vipul Bondre (MEMSYS, 2022)

WinDRAM: Weak rows as in-DRAM cache. - Sudershan Kumar; Prabuddha Sinha; Shirshendu Das (Concurr. Comput. Pract. Exp., 2022)

VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design. - Kaustav Goswami 002; Hemanta Kumar Mondal; Shirshendu Das; Dip Sankar Banerjee (CoRR, 2022)

BHT-NoC: Blaming Hardware Trojans in NoC Routers. - Bharat Bisht; Shirshendu Das (IEEE Des. Test, 2022)

Process variation aware DRAM-Cache resizing. - Bindu Agarwalla; Shirshendu Das; Nilkanta Sahu (J. Syst. Archit., 2022)

ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning. - Jaspinder Kaur; Shirshendu Das (ISQED, 2023)

TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks. - Jaspinder Kaur; Shirshendu Das (J. Syst. Archit., 2023)

Variation aware power management for GPU memories. - Divyansh Maura; Tanmay Goel; Kaustav Goswami 002; Dip Sankar Banerjee; Shirshendu Das (Microprocess. Microsystems, 2023)

edAttack: Hardware Trojan Attack on On-Chip Packet Compression. - Atul Kumar; Dipika Deb; Shirshendu Das; Palash Das (IEEE Des. Test, 2023)

$ mathcal{F}lush+early mathcal{R} text{ELOAD}$: Covert Channels Attack on Shared LLC Using MSHR Merging. - Aditya S. Gangwar; Prathamesh Nitin Tanksale; Shirshendu Das; Sudeepta Mishra (DATE, 2024)

LiveWay: Dynamic Write Bypassing for Lifetime Enhancement in STT-RAM LLC. - Prabuddha Sinha; Krishna Prathik B. V.; Shirshendu Das; Venkata Kalyan Tavva (HIPCW, 2024)

PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC. - Prabuddha Sinha; Krishna Pratik BV; Shirshendu Das; Venkata Kalyan Tavva (MEMSYS, 2024)

RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks. - Jaspinder Kaur; Shirshendu Das (ACM Trans. Design Autom. Electr. Syst., 2024)

HTree: Hardware Trojan Attack on Cache Resizing Policies. - Atul Kumar; Shirshendu Das; Basant Subba (IEEE Embed. Syst. Lett., 2024)

$ mathcal{RRR}$: Rethinking Randomized Remapping for High Performance Secured NVM LLC. - Prathamesh Nitin Tanksale; Guru Raghava S. Seethiraju; Shirshendu Das; Venkata Kalyan Tavva (HOST, 2025)

SmartDeCoup: Decoupling the STT-RAM LLC for even write distribution and lifetime improvement. - Prabuddha Sinha; Krishna Prathik B. V.; Shirshendu Das; Venkata Kalyan Tavva (J. Syst. Archit., 2025)

TENDRA: Targeted Endurance Attack on STT-RAM LLC. - Prabuddha Sinha; Mangena Likhit Sai; Shirshendu Das; Venkata Kalyan Tavva (IEEE Embed. Syst. Lett., 2025)