A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition. - Shirui Zhao; Fengwei An; Hao Yu 001 (FPT, 2019)

Energy-Efficient Machine Learning Accelerator for Binary Neural Networks. - Wei Mao 002; Zhihua Xiao; Peng Xu; Hongwei Ren; Dingbang Liu; Shirui Zhao; Fengwei An; Hao Yu 001 (ACM Great Lakes Symposium on VLSI, 2020)

A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing. - Wei Mao 002; Kai Li 024; Xinang Xie; Shirui Zhao; He Li 008; Hao Yu 001 (DATE, 2021)

9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm. - Nimish Shah; Laura Isabel Galindez Olascoaga; Shirui Zhao; Wannes Meert; Marian Verhelst (ISSCC, 2021)

DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm. - Nimish Shah; Laura Isabel Galindez Olascoaga; Shirui Zhao; Wannes Meert; Marian Verhelst (CoRR, 2021)

Discrete Samplers for Approximate Inference in Probabilistic Machine Learning. - Shirui Zhao; Nimish Shah; Wannes Meert; Marian Verhelst (DATE, 2022)

A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection. - Haoran Lyu; Fengwei An; Shirui Zhao; Wei Mao 002; Hao Yu 001 (IEEE Des. Test, 2022)

DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm. - Nimish Shah; Laura Isabel Galindez Olascoaga; Shirui Zhao; Wannes Meert; Marian Verhelst (IEEE J. Solid State Circuits, 2022)

Terahertz MIMO Enhanced Sensing DFT-s-OFDM Radar. - Shirui Zhao; Zhiqing Wei (ICCT, 2023)

TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware. - Jonas Crols; Guilherme Paim; Shirui Zhao; Marian Verhelst (DATE, 2024)

MC2A: Enabling Algorithm-Hardware Co-Design for Efficient Markov Chain Monte Carlo Acceleration. - Shirui Zhao; Jun Yin; Lingyun Yao; Martin Andraud; Wannes Meert; Marian Verhelst (CoRR, 2025)

AIA: A Customized Multi-Core RISC-V SoC for Discrete Sampling Workloads in 16 nm. - Shirui Zhao; Nimish Shah; Wannes Meert; Marian Verhelst (IEEE J. Solid State Circuits, 2025)