A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Yoshinobu Nakagome; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1991)

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1992)