A single parity check forward error correction method for high speed I/O. - Shiva Kiran; Sebastian Hoyos; Samuel Palermo (GlobalSIP, 2014)

A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS. - Shengchang Cai; Ehsan Zhian Tabasy; Ayman Shafik; Shiva Kiran; Sebastian Hoyos; Samuel Palermo (VLSIC, 2015)

CMOS ADC-based receivers for high-speed electrical and optical links. - Samuel Palermo; Sebastian Hoyos; Ayman Shafik; Ehsan Zhian Tabasy; Shengchang Cai; Shiva Kiran; Keytaek Lee (IEEE Commun. Mag., 2016)

A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS. - Shengchang Cai; Ehsan Zhian Tabasy; Ayman Shafik; Shiva Kiran; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2017)

A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. - Shiva Kiran; Shengchang Cai; Ying Luo 010; Sebastian Hoyos; Samuel Palermo (CICC, 2019)

Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper). - Julian Camilo Gomez Diaz; Shiva Kiran; Samuel Palermo; Sebastian Hoyos (MWSCAS, 2019)

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. - Shiva Kiran; Shengchang Cai; Ying Luo 010; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2019)

A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS. - Yuanming Zhu; Shengchang Cai; Shiva Kiran; Yang-Hang Fan; Po-Hsuan Chang; Sebastian Hoyos; Samuel Palermo (CICC, 2020)

A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS. - Shiva Kiran; Ajay Balankutty; Yutao Liu; Rajeev Dokania; Hariprasath Venkataraman; Priya Wali; Stephen Kim; Yoel Krupnik; Ariel Cohen 001; Frank O'Mahony (VLSI Circuits, 2021)

A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET. - Yuanming Zhu; Tong Liu; Srujan Kumar Kaile; Shiva Kiran; Il-Min Yi; Ruida Liu; Julian Camilo Gomez Diaz; Sebastian Hoyos; Samuel Palermo (CICC, 2022)

A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation. - Yoav Segal; Amir Laufer; Ahmad Khairi; Yoel Krupnik; Marco Cusmai; Itamar Levin; Ari Gordon; Yaniv Saban; Vitali Rahinskj; Gadi Ori; Noam Familia; Stas Litski; et al. (ISSCC, 2022)

A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. - Ahmad Khairi; Yoel Krupnik; Amir Laufer; Yoav Segal; Marco Cusmai; Itamar Levin; Ari Gordon; Yaniv Sabag; Vitali Rahinski; Idan Lotan; Gadi Ori; Noam Familia; et al. (IEEE J. Solid State Circuits, 2023)

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET. - Yuanming Zhu; Tong Liu; Srujan Kumar Kaile; Shiva Kiran; Il-Min Yi; Ruida Liu; Julian Camilo Gomez Diaz; Sebastian Hoyos; Samuel Palermo (IEEE J. Solid State Circuits, 2023)