A class of downsampled floating tap DFE architectures with application to serial links. - Pervez M. Aziz; Hiroshi Kimura; Amaresh V. Malipatil; Shiva Kotagiri (ISCAS, 2012)

Shift register multi-phase clock based downsampled floating tap DFE for serial links. - Pervez M. Aziz; Hiroshi Kimura; Amaresh V. Malipatil; Shiva Kotagiri; Gordon Chan; Hairong Gao (ISCAS, 2014)

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. - Hiroshi Kimura; Pervez M. Aziz; Tai Jing; Ashutosh Sinha; Ram Narayan; Hairong Gao; Ping Jing; Gary Hom; Anshi Liang; Eric Zhang; Aniket Kadkol; Ruchi Kothari; et al. (ISSCC, 2014)

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. - Hiroshi Kimura; Pervez M. Aziz; Tai Jing; Ashutosh Sinha; Shiva Prasad Kotagiri; Ram Narayan; Hairong Gao; Ping Jing; Gary Hom; Anshi Liang; Eric Zhang; Aniket Kadkol; et al. (IEEE J. Solid State Circuits, 2014)