Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model. - Shivendra Singh Parihar; Ramchandra Gurjar (VDAT, 2019)

Self-Heating characterization and modeling of 5nm technology node FinFETs. - Shivendra Singh Parihar; Jun Z. Huang; Weike Wang; Kimihiko Imura; Yogesh Singh Chauhan (DRC, 2022)

Design Automation for Cryogenic CMOS Circuits. - Victor M. van Santen; Marcel Walter; Florian Klemme; Shivendra Singh Parihar; Girish Pahwa; Yogesh Singh Chauhan; Robert Wille; Hussam Amrouch (DAC, 2023)

5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing. - Shivendra Singh Parihar; Simon Thomann; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (DRC, 2023)

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs. - Shivendra Singh Parihar; Simon Thomann; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (IEEE Open J. Circuits Syst., 2023)

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K. - Shivendra Singh Parihar; Victor M. van Santen; Simon Thomann; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction. - Shivendra Singh Parihar; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (IRPS, 2024)

Technology Mapping for Cryogenic CMOS Circuits. - Benjamin Hien; Marcel Walter; Victor M. van Santen; Florian Klemme; Shivendra Singh Parihar; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch; Robert Wille (ISVLSI, 2024)

Energy-Efficient Cryogenic Ternary Content Addressable Memory using Ferroelectric SQUID. - Shamiul Alam; Simon Thomann; Shivendra Singh Parihar; Yogesh Singh Chauhan; Kai Ni 004; Hussam Amrouch; Ahmedullah Aziz (CoRR, 2024)

Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic Computing. - Mahdi Benkhelifa; Shivendra Singh Parihar; Anirban Kar; Girish Pahwa; Yogesh Singh Chauhan; Hussam Amrouch (DATE, 2025)

Benchmarking Cryogenic Circuits using 5 nm FinFETs for Quantum Processing. - Anirban Kar; Shivendra Singh Parihar; Florian Klemme; Yogesh Singh Chauhan; Hussam Amrouch (ISCAS, 2025)

Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs. - Divya Praneetha Ravipati; Victor M. van Santen; Shivendra Singh Parihar; Yogesh Singh Chauhan; Preeti Ranjan Panda; Hussam Amrouch (IEEE Trans. Computers, 2025)