A Single-Ended Read Decoupled 9T SRAM Cell for Low Power Applications. - Shivram Mansore; Radheshyam Gamad; D. K. Mishra (iNIS, 2017)

A data-aware write-assist 10T SRAM cell with bit-interleaving capability. - Shivram Mansore; Radheshyam Gamad (Turkish J. Electr. Eng. Comput. Sci., 2018)