Research on Inferring ELECTRE-III's Parameters with Fuzzy Information and a Case on Naval Gun Weapon System Integration. - Shiyan Sun; Hangyu Wang; Zhiming Qiu (FSKD (1), 2007)

A New Fuzzy Weapon System Optimal Design Method with Power Index. - Shiyan Sun; Guoqing Yu; Hangyu Wang (FSKD (4), 2009)

A New Method for Optimal Configuration of Weapon System. - Dechao Zhou; Shiyan Sun; Qiang Wang (ISICA, 2009)

On a Computational Method for Impact of Compressible Fluid. - Shili Sun; Shiyan Sun; Jian Hu (CSO, 2012)

A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOS. - An'an Li; Yingtao Ding; Zipeng Chen; Wei Wang; Sijia Jiang; Shiyan Sun; Zhiming Chen 001; Baoyong Chi (A-SSCC, 2019)

A Highly-Integrated Ka-Band Direct Up-Conversion Transmitter for Satellite Communication in 65nm CMOS. - Jinyu Zhu; Shiyan Sun; Baoyong Chi; Guangnan Zou; Yanfeng Wang (ICCT, 2020)

A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS. - An'an Li; Min Lin 002; Baoyong Chi; Yingtao Ding; Zheng Song 002; Zipeng Chen; Shiyan Sun; Yutian Li; Yinghang Wu; Zhenwu Wang; Zhiming Chen 001 (IEEE Access, 2020)

An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator. - Wei Deng 001; Haikun Jia; Rui Wu 001; Shiyan Sun; Chenggang Li; Zhihua Wang 001; Baoyong Chi (CICC, 2021)

Research on Data Fusion for Flight Reliability Evaluation of Guided Munitions. - Yusen Cheng; Shiyan Sun; Yaqin Zeng; Xuan Wang; Lin Li (IMMS, 2021)

A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth. - Wei Deng 001; Zipeng Chen; Haikun Jia; Shiyan Sun; Guopei Chen; Zhihua Wang 001; Baoyong Chi (VLSI Circuits, 2021)

A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS. - Zipeng Chen; Wei Deng 001; Haikun Jia; Pingda Guan; Taikun Ma; Shiyan Sun; Xiangrong Huang; Guopei Chen; Ruichang Ma; Shengnan Dong; Luqiang Duan; Zhihua Wang 001; et al. (VLSI Circuits, 2021)

Space-address decoupled scratchpad memory management for neural network accelerators. - Zhenxing Zhang; Shiyan Sun; Xunyu Chen; Tian Zhi; Qi Guo 001; Yunji Chen (Concurr. Comput. Pract. Exp., 2021)

A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiyan Sun; Qixiu Wu; Jiajie Tang; Zhihua Wang 001; Baoyong Chi (ESSCIRC, 2022)

Deep Flow-Guided Video Dehazing Based on Multi-scale Recurrent Network. - Shiyan Sun; Yongfang Wang; Tengyao Cui; Zhijun Fang (IFTC, 2022)

An improved Monte Carlo localization using optimized iterative closest point for mobile robots. - Wenjian Ying; Shiyan Sun (Cogn. Comput. Syst., 2022)

A Ka-band calibratable phased-array front-end chip with high element-consistency. - Shiyan Sun; An'an Li; Yingtao Ding; Zipeng Chen; Wei Wang; Sijia Jiang; Zhiming Chen 001; Baoyong Chi (Sci. China Inf. Sci., 2022)

A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation. - Wei Deng 001; Zipeng Chen; Haikun Jia; Angxiao Yan; Shiyan Sun; Guopei Chen; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2022)

A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology. - Pingda Guan; Haikun Jia; Wei Deng 001; Ruichang Ma; Mingxing Deng; Jiamin Xue; Angxiao Yan; Shiyan Sun; Zhihua Wang 001; Baoyong Chi (A-SSCC, 2023)

A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. - Shiwei Zhang; Wei Deng 001; Haikun Jia; Hongzhuo Liu; Shiyan Sun; Pingda Guan; Baoyong Chi (CICC, 2023)

Transceiver SoC for Wireless Indoor Sensing Data-fusion. - Bufan Zhu; Wei Deng 001; Ziying Huang; Haikun Jia; Haiyang Jia; Angxiao Yan; Yumeng Yang; Junfeng Liu; Yu Fu; Shiyan Sun; Chao Tang; Taikun Ma; et al. (CICC, 2023)

A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiwei Zhang; Shiyan Sun; Baoyong Chi (ESSCIRC, 2023)

An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. - Angxiao Yan; Wei Deng 001; Haikun Jia; Shiyan Sun; Chao Tang; Bufan Zhu; Yu Fu; Hongzhuo Liu; Baoyong Chi (VLSI Technology and Circuits, 2023)

An Intelligent Classification Approach via Multiple Classifier Fusion and Its Application to the Fault Diagnosis. - Lin Li; Shiyan Sun; Yaqin Zeng; Zhangsong Shi; Xuan Wang (IEEE Access, 2023)

A D-Band Joint Radar-Communication CMOS Transceiver. - Wei Deng 001; Zipeng Chen; Haikun Jia; Pingda Guan; Taikun Ma; Angxiao Yan; Shiyan Sun; Xiangrong Huang; Guopei Chen; Ruichang Ma; Shengnan Dong; Luqiang Duan; et al. (IEEE J. Solid State Circuits, 2023)

An Improved Method for Predicting the Remaining Useful Life Using a Spatial-Temporal Feature Extraction Network With Attention Mechanism. - Xiaojia Yan; Weige Liang; Shiyan Sun (IEEE Access, 2024)

A Multireference PLL: Theory and Implementation. - Hongzhuo Liu; Wei Deng 001; Haikun Jia; Shiwei Zhang; Shiyan Sun; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2024)

A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. - Pingda Guan; Ruichang Ma; Haikun Jia; Wei Deng 001; Mingxing Deng; Jiamin Xue; Angxiao Yan; Shiyan Sun; Qiuyu Peng; Teerachot Siriburanon; Robert Bogdan Staszewski; Zhihua Wang 001; et al. (IEEE J. Solid State Circuits, 2024)

ReWind: Understanding Long Videos with Instructed Learnable Memory. - Anxhelo Diko; Tinghuai Wang; Wassim Swaileh; Shiyan Sun; Ioannis Patras (CVPR, 2025)

19.9 An 11-to-16.4GHz, 3.4GHz/µs-Slope, 5.32GHz-Chirp-Bandwidth, 0.043%-RMS-Frequency-Error FMCW Digital PLL with Posterior-Segment DPD Featuring 5-Chirp-Cycle Convergence Time. - Angxiao Yan; Wei Deng 001; Haikun Jia; Yumeng Yang; Chao Tang; Shiyan Sun; Zhihua Wang 001; Baoyong Chi (ISSCC, 2025)

Distributed Fixed-Time Cooperative Guidance Law for Simultaneous Attack With Impact Angle Constraint. - Yu Zhang; Shiyan Sun (IEEE Access, 2025)

Time - Frequency Mixed-Domain Impedance Inversion for Nonstationary Seismic Based on Frequency-Dependent Q. - Zhidi An; Xiaotao Wen; Shiyan Sun; Bo Li 142; Yuqiang Zhang (IEEE Trans. Geosci. Remote. Sens., 2025)

A Transformer-Based Series-Resonance CMOS VCO. - Shiwei Zhang; Wei Deng 001; Haikun Jia; Hongzhuo Liu; Shiyan Sun; Pingda Guan; Zhihua Wang 001; Baoyong Chi (IEEE J. Solid State Circuits, 2025)

A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z-Compliant Joint-Radar-Communication-Location Transceiver SoC. - Bufan Zhu; Wei Deng 001; Ziying Huang; Haikun Jia; Haiyang Jia; Angxiao Yan; Yumeng Yang; Junfeng Liu; Yu Fu; Shiyan Sun; Chao Tang; Lixue Kuang; et al. (IEEE J. Solid State Circuits, 2025)