A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. - Shiyu Su; Tu-I Tsai; Praveen Kumar Sharma; Mike Shuo-Wei Chen (VLSIC, 2014)

A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. - Shiyu Su; Tu-I Tsai; Praveen Kumar Sharma; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2015)

27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. - Shiyu Su; Mike Shuo-Wei Chen (ISSCC, 2016)

A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS. - Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2016)

A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. - Shiyu Su; Mike Shuo-Wei Chen (ISSCC, 2018)

A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands. - Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2018)

A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. - Shiyu Su; Mike Shuo-Wei Chen (VLSI Circuits, 2019)

Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. - Juzheng Liu; Mohsen Hassanpourghadi; Qiaochu Zhang; Shiyu Su; Mike Shuo-Wei Chen (ICCAD, 2020)

CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. - Qiaochu Zhang; Shiyu Su; Juzheng Liu; Mike Shuo-Wei Chen (ICCAD, 2020)

Millimeter-Wave Communications with Beamforming for UAV-Assisted Railway Monitoring System. - Shiyu Su (IoTaaS, 2020)

10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. - Shiyu Su; Mike Shuo-Wei Chen (ISSCC, 2020)

Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. - Mohsen Hassanpourghadi; Shiyu Su; Rezwan A. Rasul; Juzheng Liu; Qiaochu Zhang; Mike Shuo-Wei Chen (DAC, 2021)

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. - Juzheng Liu; Shiyu Su; Meghna Madhusudan; Mohsen Hassanpourghadi; Samuel Saunders; Qiaochu Zhang; Rezwan A. Rasul; Yaguang Li; Jiang Hu; Arvind Kumar Sharma; Sachin S. Sapatnekar; Ramesh Harjani; et al. (ICCAD, 2021)

29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. - Qiaochu Zhang; Shiyu Su; Cheng-Ru Ho; Mike Shuo-Wei Chen (ISSCC, 2021)

A Time-Approximation Filter for Direct RF Transmitter. - Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2021)

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. - Shiyu Su; Qiaochu Zhang; Mohsen Hassanpourghadi; Juzheng Liu; Rezwan A. Rasul; Mike Shuo-Wei Chen (ASP-DAC, 2022)

TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. - Shiyu Su; Qiaochu Zhang; Juzheng Liu; Mohsen Hassanpourghadi; Rezwan A. Rasul; Mike Shuo-Wei Chen (ASP-DAC, 2022)

High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. - Shiyu Su; Mike Shuo-Wei Chen (CICC, 2022)

A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. - Qiaochu Zhang; Shiyu Su; Mike Shuo-Wei Chen (DAC, 2022)

SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. - Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2022)

A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. - Qiaochu Zhang; Shiyu Su; Cheng-Ru Ho; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2022)

A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. - Hsiang-Chun Cheng; Shiyu Su; Mayank Palaria; Qiaochu Zhang; Ce Yang; Sushmit Hossain; Ryan M. Bena; Buyun Chen; Zerui Liu; Juzheng Liu; Rezwan A. Rasul; Quan Nguyen 004; et al. (CICC, 2023)

A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. - Shiyu Su; Qiaochu Zhang; Mike Shuo-Wei Chen (CICC, 2023)

Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. - Mayank Palaria; Shiyu Su; Hsiang-Chun Cheng; Rezwan A. Rasul; Qiaochu Zhang; Soumya Mahapatra; Chong-Fatt Law; Sushmit Hossain; Ryan M. Bena; Wei Wu; Quan Nguyen 004; Mike Shuo-Wei Chen (ESSCIRC, 2023)

A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. - Qiaochu Zhang; Hsiang-Chun Cheng; Shiyu Su; Mike Shuo-Wei Chen (ISSCC, 2023)

Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter. - Ce Yang; Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2023)

Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET. - Qiaochu Zhang; Shiyu Su; Baishakhi Rani Biswas; Sandeep Gupta 001; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)

A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. - Qiaochu Zhang; Shiyu Su; Zerui Liu; Hsiang-Chun Cheng; Zhengyi Qiu; Mayank Palaria; Jiacheng Ye; Deming Meng; Buyun Chen; Sushmit Hossain; Wei Wu; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)

Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. - Qiaochu Zhang; Hsiang-Chun Cheng; Shiyu Su; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2024)

26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS. - Soumya Mahapatra; Mostafa M. Ayesh; Ce Yang; Mayank Palaria; Shiyu Su; Aoyang Zhang; Mike Shuo-Wei Chen (ISSCC, 2025)

11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS. - Ce Yang; Shiyu Su; Mostafa M. Ayesh; Soumya Mahapatra; Maysara Hamada; Vinay Chenna; Hossein Hashemi 001; Mike Shuo-Wei Chen (ISSCC, 2025)

Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adders. - Shiyu Su; Qiaochu Zhang; Baishakhi Rani Biswas; Sandeep K. Gupta 001; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2025)