Chip assemblers: Concepts and capabilities. - Randy H. Katz; Shlomo Weiss (DAC, 1983)

Recovery of In-Memory Data Structures for Interactive Update Applications. - Shlomo Weiss (COMPCON, 1984)

Design transaction management. - Randy H. Katz; Shlomo Weiss (DAC, 1984)

Instruction Issue Logic in Pipelined Supercomputers. - Shlomo Weiss; James E. Smith 001 (IEEE Trans. Computers, 1984)

DOSS: a storage system for design data. - Shlomo Weiss; Katie Rotzell; Tom Rhyne; Arny Goldfein (DAC, 1986)

A Simulation Study of Decoupled Architecture Computers. - James E. Smith 001; Shlomo Weiss; Nicholas Y. Pang (IEEE Trans. Computers, 1986)

An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors. - Shlomo Weiss (ISCA, 1989)

Scalar supercomputer architecture. - Shlomo Weiss (Proc. IEEE, 1989)

A study of scalar compilation techniques for pipelined supercomputers. - Shlomo Weiss; James E. Smith 001 (ACM Trans. Math. Softw., 1990)

Multiple-Port Memory Access in Decoupled Architecture Processors. - Shlomo Weiss (ICPP (1), 1991)

Memory conflict resolution in vector supercomputers. - Shlomo Weiss (J. Supercomput., 1992)

Scalar Memory References in Pipelined Multiprocessors: A Performance Study. - Ravi Ganesan; Shlomo Weiss (IEEE Trans. Software Eng., 1992)

Optimizing a superscalar machine to run vector code. - Shlomo Weiss (IEEE Parallel Distributed Technol. Syst. Appl., 1993)

PowerPC 601 and Alpha 21064: A Tale of Two RISCs. - James E. Smith 001; Shlomo Weiss (Computer, 1994)

Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors. - Shlomo Weiss (HPCA, 1995)

Branch Prediction Based on Universal Data Compression Algorithms. - Eitan Federovsky; Meir Feder; Shlomo Weiss (ISCA, 1998)

Floating point micropipeline performance. - Shlomo Weiss; A. Goldstein (J. Syst. Archit., 1998)

Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes. - Shlomo Reches; Shlomo Weiss (IEEE Trans. Computers, 1998)

Extending PCI Performance Beyond the Desktop. - Shlomo Weiss; Ehud Finkelstein (Computer, 1999)

Microprocessor system buses: A case study. - Ehud Finkelstein; Shlomo Weiss (J. Syst. Archit., 1999)

HW/SW partitioning of an embedded instruction memory decompressor. - Shlomo Weiss; Shay Beren (CODES, 2001)

A study of CodePack: optimizing embedded code space. - Avishay Orpaz; Shlomo Weiss (CODES, 2002)

A PCI bus simulation framework and some simulation results on PCI standard 2.1 latency limitations. - Ehud Finkelstein; Shlomo Weiss (J. Syst. Archit., 2002)

Pattern Matching by means of Multi-Resolution Compression. - Avishay Orpaz; Shlomo Weiss (DCC, 2003)

Approximate prefix coding for system-on-a-chip programs. - Shlomo Weiss; Roman Tsikel (J. Syst. Archit., 2003)

Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors. - Shlomo Weiss; Shay Beren (IEEE Trans. Computers, 2003)

Embedded instruction memory in automotive engine controllers. - Tal Oved; Shlomo Weiss (IEEE Trans. Veh. Technol., 2003)

Selective main memory compression by identifying program phase changes. - Doron Nakar; Shlomo Weiss (WMPI, 2004)

Programming Windows NT device drivers to operate non-interrupting embedded devices. - Tomer Karin; Shlomo Weiss (Microprocess. Microsystems, 2004)

Fairness and Throughput in Switch on Event Multithreading. - Ron Gabor; Shlomo Weiss; Avi Mendelson (MICRO, 2006)

Power-aware out-of-order issue logic in high-performance microprocessors. - Yehuda Sadeh Weinraub; Shlomo Weiss (Microprocess. Microsystems, 2006)

Fairness enforcement in switch on event multithreading. - Ron Gabor; Shlomo Weiss; Avi Mendelson (ACM Trans. Archit. Code Optim., 2007)

DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. - Amit Golander; Shlomo Weiss; Ronny Ronen (IEEE Comput. Archit. Lett., 2008)

Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers. - Roger Kahn; Shlomo Weiss (Microprocess. Microsystems, 2008)

Hiding the misprediction penalty of a resource-efficient high-performance processor. - Amit Golander; Shlomo Weiss (ACM Trans. Archit. Code Optim., 2008)

Service level agreement for multithreaded processors. - Ron Gabor; Avi Mendelson; Shlomo Weiss (ACM Trans. Archit. Code Optim., 2009)

Checkpoint allocation and release. - Amit Golander; Shlomo Weiss (ACM Trans. Archit. Code Optim., 2009)

Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. - Amit Golander; Shlomo Weiss; Ronny Ronen (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Reexecution and Selective Reuse in Checkpoint Processors. - Amit Golander; Shlomo Weiss (Trans. High Perform. Embed. Archit. Compil., 2009)

Low power branch prediction for embedded application processors. - Nadav Levison; Shlomo Weiss (ISLPED, 2010)

Reducing leakage power with BTB access prediction. - Roger Kahn; Shlomo Weiss (Integr., 2010)

Branch target buffer design for embedded processors. - Nadav Levison; Shlomo Weiss (Microprocess. Microsystems, 2010)

Streamlined Network-on-Chip for Multicore Embedded Architectures. - Gadi Oxman; Shlomo Weiss; Yitzhak (Tsahi) Birk (ARCS, 2012)

Buffered deflection routing for networks-on-chip. - Gadi Oxman; Shlomo Weiss; Yitzhak (Tsahi) Birk (INA-OCMC@HiPEAC, 2012)

Virtio network paravirtualization driver: Implementation and performance of a de-facto standard. - Gal Motika; Shlomo Weiss (Comput. Stand. Interfaces, 2012)

Architectural virtualization extensions: A systems perspective. - Simon Grinberg; Shlomo Weiss (Comput. Sci. Rev., 2012)

Complex Floating Point - A Novel Data Word Representation for DSP Processors. - Nadav Cohen 001; Shlomo Weiss (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Parallel Algorithm for a Physiological Non-Linear Model of the Cochlea. - Doron Sabo; Shlomo Weiss; Miriam Furst (ICCS, 2013)

Phase-change memory: An architectural perspective. - Omer Zilberberg; Shlomo Weiss; Sivan Toledo (ACM Comput. Surv., 2013)

Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores. - Eran Shifer; Shlomo Weiss (ACM Trans. Archit. Code Optim., 2013)

RIDER: Ring deflection router with buffers. - Gadi Oxman; Shlomo Weiss (Des. Autom. Embed. Syst., 2014)

Fast evaluation of a time-domain non-linear cochlear model on GPUs. - Doron Sabo; Oded Barzelay; Shlomo Weiss; Miriam Furst (J. Comput. Phys., 2014)

Computational methods for Conway's Game of Life cellular automaton. - Gadi Oxman; Shlomo Weiss; Yair Be'ery (J. Comput. Sci., 2014)

Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators. - Sagi Manole; Amit Golander; Shlomo Weiss (IEEE Trans. Computers, 2014)

L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters. - Alexei Jolondz; Shlomo Weiss; Amit Golander (IEEE Trans. Very Large Scale Integr. Syst., 2014)

DNOC: an accurate and fast virtual channel and deflection routing network-on-chip simulator. - Gadi Oxman; Shlomo Weiss (ISPASS, 2015)

Deflection Routing in Hierarchical Mesh NoCs. - Gadi Oxman; Shlomo Weiss (IEEE Embed. Syst. Lett., 2016)

An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation. - Gadi Oxman; Shlomo Weiss (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Decoupled Branch Predictor for Embedded DSP. - Konstantin Berestizshevsky; Shlomo Weiss (IEEE Embed. Syst. Lett., 2018)

SiMT-DSP: A Massively Multithreaded DSP Architecture. - Ben Perach; Shlomo Weiss (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Perceptron based filtering of futile prefetches in embedded VLIW DSPs. - David Uzan; Roger Kahn; Shlomo Weiss (J. Syst. Archit., 2020)

A novel low power hybrid cache using GC-EDRAM cells. - Junyi Zhou; Roger Kahn; Shlomo Weiss (Integr., 2021)