HOPLA-PLA optimization and synthesis. - Shmuel Wimer; N. Sharfman (DAC, 1983)

Optimal Chaining of CMOS Transistors in a Functional Cell. - Shmuel Wimer; Ron Y. Pinter; Jack A. Feldman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Analysis of strategies for constructive general block placement. - Shmuel Wimer; Israel Koren (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation. - Reuven Bar-Yehuda; Jack A. Feldman; Ron Y. Pinter; Shmuel Wimer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Optimal aspect ratios of building blocks in VLSI. - Shmuel Wimer; Israel Koren; Israel Cederbaum (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Balanced Block Spacing for VLSI Layout. - Israel Cederbaum; Israel Koren; Shmuel Wimer (Discret. Appl. Math., 1992)

On Paths with the Shortest Average Arc Length in Weighted Graphs. - Shmuel Wimer; Israel Koren; Israel Cederbaum (Discret. Appl. Math., 1993)

An efficient algorithm for some multirow layout problems. - Jack A. Feldman; Israel A. Wagner; Shmuel Wimer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Optimal resizing of bus wires in layout migration. - Shay Michaely; Shmuel Wimer; Avinoam Kolodny (ICECS, 2004)

Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. - Konstantin Moiseev; Shmuel Wimer; Avinoam Kolodny (ISCAS, 2006)

Optimal bus sizing in migration of processor design. - Shmuel Wimer; Shay Michaely; Konstantin Moiseev; Avinoam Kolodny (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

On optimal ordering of signals in parallel wire bundles. - Konstantin Moiseev; Shmuel Wimer; Avinoam Kolodny (Integr., 2008)

Timing-aware power-optimal ordering of signals. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (ACM Trans. Design Autom. Electr. Syst., 2008)

Power-delay optimization in VLSI microprocessors by wire spacing. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (ACM Trans. Design Autom. Electr. Syst., 2009)

Interconnect power and delay optimization by dynamic programming in gridded design rules. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (ISPD, 2010)

Interconnect Bundle Sizing Under Discrete Design Rules. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. - Ran Manevich; Israel Cidon; Avinoam Kolodny; Isask'har Walter; Shmuel Wimer (DSD, 2011)

The Wiener maximum quadratic assignment problem. - Eranda Çela; Nina S. Schmuck; Shmuel Wimer; Gerhard J. Woeginger (Discret. Optim., 2011)

Using well-solvable quadratic assignment problems for VLSI interconnect applications. - Ben Emanuel; Shmuel Wimer; Gershon Wolansky (Discret. Appl. Math., 2012)

The complexity of VLSI power-delay optimization by interconnect resizing. - Konstantin Moiseev; Avinoam Kolodny; Shmuel Wimer (J. Comb. Optim., 2012)

The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating. - Shmuel Wimer; Israel Koren (IEEE Trans. Very Large Scale Integr. Syst., 2012)

On optimal flip-flop grouping for VLSI power minimization. - Shmuel Wimer (Oper. Res. Lett., 2013)

A low energy dual-mode adder. - Shmuel Wimer; Amir Albeck; Israel Koren (Comput. Electr. Eng., 2014)

Easy and difficult exact covering problems arising in VLSI power reduction by clock gating. - Shmuel Wimer (Discret. Optim., 2014)

Cell-based interconnect migration by hierarchical optimization. - Eugene Shaphir; Ron Y. Pinter; Shmuel Wimer (Integr., 2014)

Planar CMOS to multi-gate layout conversion for maximal fin utilization. - Shmuel Wimer (Integr., 2014)

Using well-solvable minimum cost exact covering for VLSI clock energy minimization. - Shmuel Wimer; Doron Gluzer; Uri Wimer (Oper. Res. Lett., 2014)

A Low Energy and High Performance ${ rm DM}^{2}$ Adder. - Itamar Levi; Amir Albeck; Alexander Fish; Shmuel Wimer (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops. - Shmuel Wimer; Arye Albahari (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. - Shmuel Wimer; Israel Koren (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. - Konstantin Moiseev; Shmuel Wimer; Avinoam Kolodny (Integr., 2015)

Energy efficient hybrid adder architecture. - Shmuel Wimer; Amnon Stanislavsky (Integr., 2015)

Mixing Drivers in Clock-Tree for Power Supply Noise Reduction. - Yakov Kaplan; Shmuel Wimer (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Energy efficient deeply fused dot-product multiplication architecture. - Shmuel Wimer; Israel Koren (ASAP, 2016)

Energy efficient computing by multi-mode addition. - Amir Albeck; Shmuel Wimer (Integr., 2016)

Optimal weight allocation in rooted trees. - Shmuel Wimer (J. Comb. Optim., 2016)

Optimal VLSI Delay Tuning by Wire Shielding. - Binyamin Frankel; Shmuel Wimer (J. Optim. Theory Appl., 2016)

Opportunistic Refreshing Algorithm for eDRAM Memories. - Amit Kazimirsky; Shmuel Wimer (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree Application. - Eyal Sarfati; Binyamin Frankel; Yitzhak Birk; Shmuel Wimer (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Probability-Driven Multibit Flip-Flop Integration With Clock Gating. - Doron Gluzer; Shmuel Wimer (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Optimal queuing-based memory refreshing algorithm for energy efficient processors. - Roi Herman; Binyamin Frankel; Shmuel Wimer (Comput. Electr. Eng., 2018)

Queuing-Based eDRAM Refreshing for Ultra-Low Power Processors. - Binyamin Frankel; Roi Herman; Shmuel Wimer (IEEE Trans. Computers, 2018)

Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator. - Eyal Sarfati; Binyamin Frankel; Yitzhak Birk; Shmuel Wimer (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Resource allocation in rooted trees subject to sum constraints and nonlinear cost functions. - Nir Halman; Shmuel Wimer (Inf. Process. Lett., 2021)

A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories. - Binyamin Frankel; Shmuel Wimer (IEEE Trans. Computers, 2023)

Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAM. - Binyamin Frankel; Eyal Sarfati; Davide Rossi; Shmuel Wimer (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)