Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. - Naoya Azuma; Shunsuke Shimazaki; Noriyuki Miura; Makoto Nagata; Tomomitsu Kitamura; Satoru Takahashi; Motoki Murakami; Kazuaki Hori; Atsushi Nakamura; Kenta Tsukamoto; Mizuki Iwanami; Eiji Hankui; et al. (EMC Compo, 2013)

In-band spurious attenuation in LTE-class RFIC chip using a soft magnetic thin film. - Sho Muroga; Y. Shimada; Yasushi Endo; Satoshi Tanaka; Masahiro Yamaguchi; Naoya Azuma; Makoto Nagata; Motoki Murakami; Kazuaki Hori; Satoru Takahashi (EMC Compo, 2013)

Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. - Naoya Azuma; Shunsuke Shimazaki; Noriyuki Miura; Makoto Nagata; Tomomitsu Kitamura; Satoru Takahashi; Motoki Murakami; Kazuaki Hori; Atsushi Nakamura; Kenta Tsukamoto; Mizuki Iwanami; Eiji Hankui; et al. (IEICE Trans. Electron., 2014)

Analysis of on-chip digital noise coupling path for wireless communication IC test chip. - Satoshi Tanaka; Peng Fan; Jingyan Ma; Hanae Aoki; Masahiro Yamaguchi; Makoto Nagata; Sho Muroga (EMC Compo, 2015)

A charge recycling stacked I/O in standard CMOS technology for wide TSV data bus. - Takefumi Yoshikawa; Tatsuya Iwata; Junji Shibazaki; Sho Muroga; Hiroaki Ikeda (IEICE Electron. Express, 2020)

Effect of Complex Permeability on Circuit Parameters of CPW with Magnetic Noise Suppression Sheet. - Sho Muroga; Motoshi Tanaka; Takefumi Yoshikawa; Yasushi Endo (IEICE Trans. Commun., 2020)