Shoaib Akram

Orcid: 0000-0003-2388-0517

Affiliations:
  • Australian National University, Canberra, ACT, Australia


According to our database1, Shoaib Akram authored at least 26 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2023
Analyzing and Improving the Scalability of In-Memory Indices for Managed Search Engines.
Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023

TeraHeap: Reducing Memory Pressure in Managed Big Data Frameworks.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Scale-Model Architectural Simulation.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2021
Reliability-aware Garbage Collection for Hybrid HBM-DRAM Memories.
ACM Trans. Archit. Code Optim., 2021

Performance Evaluation of Intel Optane Memory for Managed Workloads.
ACM Trans. Archit. Code Optim., 2021

Freeing Compute Caches from Serialization and Garbage Collection in Managed Big Data Analytics.
CoRR, 2021

Scale-Model Simulation.
IEEE Comput. Archit. Lett., 2021

Exploiting Intel optane persistent memory for full text search.
Proceedings of the ISMM '21: 2021 ACM SIGPLAN International Symposium on Memory Management, 2021

2019
Crystal Gazer: Profile-Driven Write-Rationing Garbage Collection for Hybrid Memories.
Proc. ACM Meas. Anal. Comput. Syst., 2019

To expose, or not to expose, hardware heterogeneity to runtimes.
Proceedings of the Conference Companion of the 3rd International Conference on Art, 2019

RPPM: Rapid Performance Prediction of Multithreaded Workloads on Multicore Processors.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Emulating and Evaluating Hybrid Memory for Managed Languages on NUMA Hardware.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2018
Emulating Hybrid Memory on NUMA Hardware.
CoRR, 2018

RPPM: Rapid Performance Prediction of Multithreaded Applications on Multicore Hardware.
IEEE Comput. Archit. Lett., 2018

Managing hybrid memories by predicting object write intensity.
Proceedings of the Conference Companion of the 2nd International Conference on Art, 2018

Write-rationing garbage collection for hybrid memories.
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

2017
DEP+BURST: Online DVFS Performance Prediction for Energy-Efficient Managed Language Execution.
IEEE Trans. Computers, 2017

Managed Language Runtimes on Heterogeneous Hardware: Optimizations for Performance, Efficiency and Lifetime Improvement.
Proceedings of the Companion to the first International Conference on the Art, 2017

2016
Boosting the Priority of Garbage: Scheduling Collection on Heterogeneous Multicore Processors.
ACM Trans. Archit. Code Optim., 2016

DVFS performance prediction for managed multithreaded applications.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2013
Fairness-aware scheduling on single-ISA heterogeneous multi-cores.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Understanding Scalability and Performance Requirements of I/O-Intensive Applications on Future Multicore Servers.
Proceedings of the 20th IEEE International Symposium on Modeling, 2012

Understanding and improving the cost of scaling distributed event processing.
Proceedings of the Sixth ACM International Conference on Distributed Event-Based Systems, 2012

2010
A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors.
Int. J. Reconfigurable Comput., 2010

2009
Workload adaptive shared memory multicore processors with reconfigurable interconnects.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

2008
VEBoC: Variation and error-aware design for billions of devices on a chip.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008


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