Static program transformations for efficient software model checking. - Shobha Vasudevan; Jacob A. Abraham (IFIP Congress Topical Sessions, 2004)

Efficient Model Checking of Hardware Using Conditioned Slicing. - Shobha Vasudevan; E. Allen Emerson; Jacob A. Abraham (AVoCS, 2004)

Automated mapping of pre-computed module-level test sequences to processor instructions. - S. Guramurthy; Shobha Vasudevan; Jacob A. Abraham (ITC, 2005)

Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. - Sankar Gurumurthy; Shobha Vasudevan; Jacob A. Abraham (ITC, 2006)

Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. - Shobha Vasudevan; Jacob A. Abraham; Vinod Viswanath; Jiajin Tu (MEMOCODE, 2006)

Efficient Microprocessor Verification using Antecedent Conditioned Slicing. - Shobha Vasudevan; Vinod Viswanath; Jacob A. Abraham (VLSI Design, 2007)

Improved verification of hardware designs through antecedent conditioned slicing. - Shobha Vasudevan; E. Allen Emerson; Jacob A. Abraham (Int. J. Softw. Tools Technol. Transf., 2007)

Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. - Shobha Vasudevan; Vinod Viswanath; Robert W. Sumners; Jacob A. Abraham (IEEE Trans. Computers, 2007)

Sequential equivalence checking between system level and RTL descriptions. - Shobha Vasudevan; Vinod Viswanath; Jacob A. Abraham; Jiajin Tu (Des. Autom. Embed. Syst., 2008)

STAR: Generating input vectors for design validation by static analysis of RTL. - Lingyi Liu; Shobha Vasudevan (HLDVT, 2009)

Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. - Vinod Viswanath; Shobha Vasudevan; Jacob A. Abraham (VLSI Design, 2009)

Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. - Vinod Viswanath; Shobha Vasudevan; Jacob A. Abraham (J. Low Power Electron., 2009)

GoldMine: Automatic assertion generation using data mining and static analysis. - Shobha Vasudevan; David Sheridan; Sanjay J. Patel; David Tcheng; William Tuohy; Daniel R. Johnson (DATE, 2010)

Statistical guarantees of performance for MIMO designs. - Jayanand Asok Kumar; Shobha Vasudevan (DSN, 2010)

Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs. - Jayanand Asok Kumar; Shobha Vasudevan (QEST, 2010)

Towards coverage closure: Using GoldMine assertions for generating design validation stimulus. - Lingyi Liu; David Sheridan; William Tuohy; Shobha Vasudevan (DATE, 2011)

Efficient validation input generation in RTL by hybridized source code analysis. - Lingyi Liu; Shobha Vasudevan (DATE, 2011)

Scaling probabilistic timing verification of hardware using abstractions in design source code. - Jayanand Asok Kumar; Lingyi Liu; Shobha Vasudevan (FMCAD, 2011)

Signature Pattern Covering via Local Greedy Algorithm and Pattern Shrink. - Hyungsul Kim; Sungjin Im; Tarek F. Abdelzaher; Jiawei Han 001; David Sheridan; Shobha Vasudevan (ICDM, 2011)

PRECIS: Inferring invariants using program path guided clustering. - Parth Sagdeo; Viraj Athavale; Sumant Kowshik; Shobha Vasudevan (ASE, 2011)

Automatic generation of assertions from system level design using data mining. - Lingyi Liu; David Sheridan; Viraj Athavale; Shobha Vasudevan (MEMOCODE, 2011)

Variation-Conscious Formal Timing Verification in RTL. - Jayanand Asok Kumar; Shobha Vasudevan (VLSI Design, 2011)

Coverage closure in SoC verification: Are we chasing a mirage? - Shobha Vasudevan (VTS, 2011)

Verifying dynamic power management schemes using statistical model checking. - Jayanand Asok Kumar; Shobha Vasudevan (ASP-DAC, 2012)

Using static analysis for coverage extraction fromemulation/prototyping platforms. - Viraj Athavale; Sam Hertz; Darshan Jetly; Vijay Ganesan; Jim Krysl; Shobha Vasudevan (CODES+ISSS, 2012)

Goal-oriented stimulus generation for analog circuits. - Seyed Nematollah Ahmadyan; Jayanand Asok Kumar; Shobha Vasudevan (DAC, 2012)

Early prediction of NBTI effects using RTL source code analysis. - Jayanand Asok Kumar; Kenneth M. Butler; Heesoo Kim; Shobha Vasudevan (DAC, 2012)

Word level feature discovery to enhance quality of assertion mining. - Lingyi Liu; Chen-Hsuan Lin 002; Shobha Vasudevan (ICCAD, 2012)

A Technique for Test Coverage Closure Using GoldMine. - Lingyi Liu; David Sheridan; William Tuohy; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Formal Performance Analysis for Faulty MIMO Hardware. - Jayanand Asok Kumar; Shobha Vasudevan (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm. - Seyed Nematollah Ahmadyan; Jayanand Asok Kumar; Shobha Vasudevan (DATE, 2013)

Reachability analysis of nonlinear analog circuits through iterative reachable set reduction. - Seyed Nematollah Ahmadyan; Shobha Vasudevan (DATE, 2013)

Generating concise assertions with complete coverage. - Chen-Hsuan Lin 002; Lingyi Liu; Shobha Vasudevan (ACM Great Lakes Symposium on VLSI, 2013)

Scaling RTL property checking using feasible path analysisand decomposition. - Lingyi Liu; Shobha Vasudevan (ACM Great Lakes Symposium on VLSI, 2013)

Diagnosing root causes of system level performance violations. - Lingyi Liu; Xuanyu Zhong; Xiaotao Chen; Shobha Vasudevan (ICCAD, 2013)

Using automatically generated invariants for regression testing and bug localization. - Parth Sagdeo; Nicholas Ewalt; Debjit Pal; Shobha Vasudevan (ASE, 2013)

Automatic Generation of System Level Assertions from Transaction Level Models. - Lingyi Liu; Shobha Vasudevan (J. Electron. Test., 2013)

Mining Hardware Assertions With Guidance From Static Analysis. - Samuel Hertz; David Sheridan; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Formal Probabilistic Timing Verification in RTL. - Jayanand Asok Kumar; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Code Coverage of Assertions Using RTL Source Code Analysis. - Viraj Athavale; Sai Ma; Samuel Hertz; Shobha Vasudevan (DAC, 2014)

A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions. - David Sheridan; Lingyi Liu; Hyungsul Kim; Shobha Vasudevan (VLSID, 2014)

Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions. - Jayanand Asok Kumar; Seyed Nematollah Ahmadyan; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL. - Lingyi Liu; Shobha Vasudevan (ACM Trans. Design Autom. Electr. Syst., 2014)

Fast eye diagram analysis for high-speed CMOS circuits. - Seyed Nematollah Ahmadyan; Chenjie Gu; Suriyaprakash Natarajan; Eli Chiprout; Shobha Vasudevan (DATE, 2015)

Packer classifier based on PE header information. - Qiao Jin; Jiayi Duan; Shobha Vasudevan; Michael D. Bailey (HotSoS, 2015)

Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal Selection. - Sai Ma; Debjit Pal; Rui Jiang; Sandip Ray; Shobha Vasudevan (ICCAD, 2015)

Every test makes a difference: Compressing analog tests to decrease production costs. - Seyed Nematollah Ahmadyan; Suriyaprakash Natarajan; Shobha Vasudevan (ASP-DAC, 2016)

Duplex: simultaneous parameter-performance exploration for optimizing analog circuits. - Seyed Nematollah Ahmadyan; Shobha Vasudevan (ICCAD, 2016)

Symptomatic Bug Localization for Functional Debug of Hardware Designs. - Debjit Pal; Shobha Vasudevan (VLSID, 2016)

Automated Transient Input Stimuli Generation for Analog Circuits. - Seyed Nematollah Adel Ahmadyan; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Still a Fight to Get It Right: Verification in the Era of Machine Learning. - Shobha Vasudevan (ICRC, 2017)

A novel test compression algorithm for analog circuits to decrease production costs. - Seyed Nematollah Ahmadyan; Suriyaprakash Natarajan; Shobha Vasudevan (Integr., 2017)

Automated Generation and Selection of Interpretable Features for Enterprise Security. - Jiayi Duan; Ziheng Zeng; Alina Oprea; Shobha Vasudevan (IEEE BigData, 2018)

Application level hardware tracing for scaling post-silicon debug. - Debjit Pal; Abhishek Sharma; Sandip Ray; Flavio M. de Paula; Shobha Vasudevan (DAC, 2018)

A figure of merit for assertions in verification. - Samuel Hertz; Debjit Pal; Spencer Offenberger; Shobha Vasudevan (ASP-DAC, 2019)

Guilty As Charged: Computational Reliability Threats Posed By Electrostatic Discharge-induced Soft Errors. - Keven Feng; Sandeep Vora; Rui Jiang; Elyse Rosenbaum; Shobha Vasudevan (DATE, 2019)

Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing. - Debjit Pal; Sai Ma; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Assertion Ranking Using RTL Source Code Analysis. - Debjit Pal; Spencer Offenberger; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Learning Semantic Representations to Verify Hardware Designs. - Shobha Vasudevan; Wenjie Jiang 001; David Bieber; Rishabh Singh; Hamid Shojaei; Richard Ho 001; Charles Sutton (NeurIPS, 2021)

Feature Engineering for Scalable Application-Level Post-Silicon Debugging. - Debjit Pal; Shobha Vasudevan (CoRR, 2021)

ARISTOTLE: Feature Engineering for Scalable Application-Level Post-Silicon Debugging. - Debjit Pal; Shobha Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

BAMBI integrates biostatistical and artificial intelligence methods to improve RNA biomarker discovery. - Peng Zhou; Zixiu Li; Feifan Liu; Euijin Kwon; Tien-Chan Hsieh; Shangyuan Ye; Shobha Vasudevan; Jung Ae Lee; Khanh-Van Tran; Chan Zhou (Briefings Bioinform., 2025)