Yield enhancement flow for analog and full custom designs reliability-rules automatic application. - Ahmad Abdulghany; Rami Fathy Salem; Luigi Capodieci; Shobhit Malik (IDT, 2011)

Deriving Feature Fail Rate from Silicon Volume Diagnostics Data. - Shobhit Malik; Thomas Herrmann; Sriram Madhavan; Rao Desineni; Chris Schuermyer; Geir Eide (IEEE Des. Test, 2013)

Quantified contribution of design for manufacturing to yield at 28nm. - Thomas Herrmann; Shobhit Malik; Sriram Madhavan (ETS, 2014)