SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method. - Tsukasa Yamauchi; Shogo Nakaya; Nobuki Kajihara (FCCM, 1996)

SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method. - Tsukasa Yamauchi; Shogo Nakaya; Nobuki Kajihara (Parcella, 1996)

Evolvable Hardware Chip for High Precision Printer Image Compression. - Hidenori Sakanashi; Mehrdad Salami; Masaya Iwata; Shogo Nakaya; Tsukasa Yamauchi; Takeshi Inuo; Nobuki Kajihara; Tetsuya Higuchi (AAAI/IAAI, 1998)

A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. - Isamu Kajitani; Tsutomu Hoshino; Daisuke Nishikawa; Hiroshi Yokoi; Shogo Nakaya; Tsukasa Yamauchi; Takeshi Inuo; Nobuki Kajihara; Masaya Iwata; Didier Keymeulen; Tetsuya Higuchi (ICES, 1998)

Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. - Tsukasa Yamauchi; Shogo Nakaya; Takeshi Inuo; Nobuki Kajihara (FCCM, 2000)

Arithmetic Operation Oriented Reconfigurable Chip: RHW. - Tsukasa Yamauchi; Shogo Nakaya; Takeshi Inuo; Nobuki Kajihara (FPL, 2001)

Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. - Makoto Miyamura; Shogo Nakaya; Munehiro Tada; Toshitsugu Sakamoto; Koichiro Okamoto; Naoki Banno; Shinji Ishida; Kimihiko Ito; Hiromitsu Hada; Noboru Sakimura; Tadahiko Sugibayashi; Masato Motomura (ISSCC, 2011)

Adaptive sensing of ECG signals using R-R interval prediction. - Shogo Nakaya; Yuichi Nakamura 002 (EMBC, 2013)

A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. - Shogo Nakaya; Makoto Miyamura; Noboru Sakimura; Yuichi Nakamura 002; Tadahiko Sugibayashi (IPSJ Trans. Syst. LSI Des. Methodol., 2013)