2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (ISSCC, 2007)

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (IEEE J. Solid State Circuits, 2008)

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. - Shoun Matsunaga; Jun Hayakawa; Shoji Ikeda; Katsuya Miura; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (DATE, 2009)

Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. - Fumitaka Iga; Masashi Kamiyanagi; Shoji Ikeda; Katsuya Miura; Jun Hayakawa; Haruhiro Hasegawa; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEICE Trans. Electron., 2010)

Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. - Masashi Kamiyanagi; Fumitaka Iga; Shoji Ikeda; Katsuya Miura; Jun Hayakawa; Haruhiro Hasegawa; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEICE Trans. Electron., 2010)

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. - Riichiro Takemura; Takayuki Kawahara; Katsuya Miura; Hiroyuki Yamamoto; Jun Hayakawa; Nozomu Matsuzaki; Kazuo Ono; Michihiko Yamanouchi; Kenchi Ito; Hiromasa Takahashi; Shoji Ikeda; Haruhiro Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. - Shoun Matsunaga; Masanori Natsui; Shoji Ikeda; Katsuya Miura; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (ASP-DAC, 2012)

A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. - Shoun Matsunaga; Sadahiko Miura; Hiroaki Honjou; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2012)

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keiichi Tokutome; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (VLSIC, 2012)

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (ISSCC, 2013)

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2013)

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEEE J. Solid State Circuits, 2013)

Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque. - Shunsuke Fukami; Hideo Sato; Michihiko Yamanouchi; Shoji Ikeda; Fumihiro Matsukura; Hideo Ohno (ASP-DAC, 2014)

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Hideo Sato; Shunsuke Fukami; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2015)

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (IEEE J. Solid State Circuits, 2015)

An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. - Tetsuo Endoh; Hiroki Koike; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. - Takahiro Hanyu; Tetsuo Endoh; Daisuke Suzuki; Hiroki Koike; Yitao Ma; Naoya Onizawa; Masanori Natsui; Shoji Ikeda; Hideo Ohno (Proc. IEEE, 2016)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A novel memory test system with an electromagnet for STT-MRAM testing. - Ryo Tamura; N. Watanabe; Hiroki Koike; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Soshi Sato (NVMTS, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (VLSI Circuits, 2020)

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (IEEE J. Solid State Circuits, 2021)

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability. - K. Watanabe; T. Shimada; K. Hirose; H. Shindo; D. Kobayashi; Takaho Tanigawa; Shoji Ikeda; Takamitsu Shinada; Hiroki Koike; Tetsuo Endoh; T. Makino; Takeshi Ohshima (IRPS, 2022)