Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. - Hironori Nakajo; Masanori Yamato; Shoji Kawahara; Norito Kato; Koichi Sasada; Mikiko Sato; Mitaro Namiki (PDPTA, 2003)

Implementation and Evaluation of a Thread Library for Multithreaded Architecture. - Koichi Sasada; Mikiko Sato; Shoji Kawahara; Norito Kato; Masanori Yamato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2003)

A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. - Mikiko Sato; Koichi Sasada; Shoji Kawahara; Norito Kato; Masanori Yamato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2003)

Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities. - Taku Ohsawa; Masamichi Takagi; Shoji Kawahara; Satoshi Matsushita (MICRO, 2005)