A feedback-type BiCMOS logic gate. - Yoji Nishio; Fumio Murabayashi; Shoichi Kotoku; Atsuo Watnabe; Shoji Shukuri; Katsuhiro Shimohigashi (IEEE J. Solid State Circuits, 1989)

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM. - Makoto Suzuki; Suguru Tachibana; Atsuo Watanabe; Shoji Shukuri; Hisayuki Higuchi; Takahiro Nagano; Katsuhiro Shimohigashi (IEEE J. Solid State Circuits, 1989)

The SDC cell-A novel design methodology for high-speed arithmetic modules using CMOS/BiCMOS precharged circuits. - Takehisa Hayashi; Toshio Doi; Mitsuo Asai; Kenichi Ishibashi; Shoji Shukuri; Atsuo Watanabe; Makoto Suzuki (IEEE J. Solid State Circuits, 1990)

On-Chip Multiple Superscalar Processors with Secondary Cache Memories. - M. Hanawa; Tadahiko Nishimukai; O. Nishii; Masato Suzuki; Kazuo Yano; Mitsuru Hiraki; Shoji Shukuri; Takashi Nishida (ICCD, 1991)

Quasi-complementary BiCMOS for sub-3-V digital circuits. - Kazuo Yano; Mitsuru Hiraki; Shoji Shukuri; Yasuo Onose; Mitsuru Hirao; Nagatoshi Ohki; Takashi Nishida; Koichi Seki; Katsuhiro Shimohigashi (IEEE J. Solid State Circuits, 1991)

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules. - Kazuo Yano; Mitsuru Hiraki; Shoji Shukuri; M. Hanawa; Masato Suzuki; S. Morita; A. Kawamata; Nagatoshi Ohki; Takashi Nishida; Koichi Seki (IEEE J. Solid State Circuits, 1992)

CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip. - Shoji Shukuri; Kazumasa Yanagisawa; Koichiro Ishibashi (CICC, 2001)

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. - Tsugio Takahashi; Tomonori Sekiguchi; Riichiro Takemura; Seiji Narui; Hiroki Fujisawa; Shinichi Miyatake; Makoto Morino; Koji Arai; Satoru Yamada; Shoji Shukuri; Masayuki Nakamura; Yoshitaka Tadaki; et al. (IEEE J. Solid State Circuits, 2001)

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. - Masanao Yamaoka; Kazumasa Yanagisawa; Shoji Shukuri; Katsuhiro Norisue; Koichiro Ishibashi (IEEE J. Solid State Circuits, 2002)