Over-30-GHz limiting amplifier ICs with small phase deviation for optical communication systems. - Makoto Nakamura; Yuhki Imai; Shoji Yamahata; Yohtaro Umeda (IEEE J. Solid State Circuits, 1996)

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. - Hideyuki Nosaka; Eiichi Sano; Kiyoshi Ishii; Minoru Ida; Kenji Kurishima; Shoji Yamahata; Tsugumichi Shibata; Hiroyuki Fukuyama; Mikio Yoneyama; Takatomo Enoki; Masahiro Muraguchi (IEEE J. Solid State Circuits, 2004)

Highly Reliable Submicron InP-Based HBTs with over 300-GHz ft. - Norihide Kashio; Kenji Kurishima; Yoshino K. Fukai; Shoji Yamahata (IEICE Trans. Electron., 2008)

Emitter-metal-related degradation in InP-based HBTs operating at high current density and its suppression by refractory metal. - Yoshino K. Fukai; Kenji Kurishima; Norihide Kashio; Minoru Ida; Shoji Yamahata; Takatomo Enoki (Microelectron. Reliab., 2009)