Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. - Masanori Hariyama; Shota Ishihara; Noriaki Idobata; Michitaka Kameyama (ERSA, 2008)

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. - Masanori Hariyama; Shota Ishihara; Michitaka Kameyama (IEICE Trans. Electron., 2008)

A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. - Shota Ishihara; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (ERSA, 2009)

An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. - Masanori Hariyama; Ryoto Tsuchiya; Shota Ishihara; Michitaka Kameyama (ERSA, 2010)

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Inf. Syst., 2010)

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. - Shota Ishihara; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2010)

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. - Yoshiya Komatsu; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (ASP-DAC, 2011)

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. - Shota Ishihara; Ryoto Tsuchiya; Yoshiya Komatsu; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2011)

A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? - Shota Ishihara; Noriaki Idobata; Yoshihiro Nakatani; Masanori Hariyama (J. Multiple Valued Log. Soft Comput., 2011)

A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. - Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. - Zhengfan Xia; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (ISCAS, 2012)

Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. - Zhengfan Xia; Shota Ishihara; Masanori Hariyama; Michitaka Kameyama (IEICE Trans. Electron., 2012)

Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. - Shota Ishihara; Noriaki Idobata; Masanori Hariyama; Michitaka Kameyama (J. Multiple Valued Log. Soft Comput., 2013)

A group-based scheduling method for landslide detection system with dense wireless sensor network. - Shota Ishihara; Masafumi Hashimoto; Naoki Wakamiya; Masayuki Murata 001; Yasutaka Kawamoto (ICT-DM, 2018)