SAR TDC Architecture with Self-Calibration Employing Trigger Circuit. - Yuki Ozawa; Takashi Ida; Richen Jiang; Shotaro Sakurai; Seiya Takigami; Nobukazu Tsukiji; Ryoji Shiota; Haruo Kobayashi 001 (ATS, 2017)

Architecture of high performance successive approximation time digitizer. - Takashi Ida; Yuki Ozawa; Jiang Richen; Shotaro Sakurai; Seiya Takigami; Nobukazu Tsukiji; Hirotaka Arai; Ryoji Shiota; Haruo Kobayashi 001 (ISPACS, 2017)

SAR TDC architecture for one-shot timing measurement with full digital implementation. - Yuki Ozawa; Takashi Ida; Shotaro Sakurai; Richen Jiang; Rino Takahashi; Haruo Kobayashi 001; Ryoji Shiota (ISPACS, 2017)

Study of multistage digital oscilloscope trigger circuit. - Shotaro Sakurai; Seiya Takigami; Takashi Ida; Yuki Ozawa; Nobukazu Tsukiji; Yasunori Kobori; Haruo Kobayashi 001; Ryoji Shiota (ISPACS, 2017)

Estimation of circuit component values in buck converter using efficiency curve. - Shotaro Sakurai; Nobukazu Tsukiji; Yasunori Kobori; Haruo Kobayashi 001 (ISPACS, 2017)