Shared data line technique for doubling the data transfer rate per pin of differential interfaces. - Fumitoshi Hatori; Shouhei Kousai; Yasuo Unekawa (CICC, 2001)

A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter. - Toru Tanzawa; Hiroyuki Shibayama; Ryota Terauchi; Katsumi Hisano; Hiroki Ishikuro; Shouhei Kousai; Hiroyuki Kobayashi; Hideaki Majima; Toru Takayama; Kenichi Agawa; Masayuki Koizumi; Fumitoshi Hatori (CICC, 2004)

A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations. - Daisuke Miyashita; Hiroki Ishikuro; Shouhei Kousai; Hiroyuki Kobayashi; Hideaki Majima; Kenichi Agawa; Mototsugu Hamada (CICC, 2005)

A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters. - Toru Tanzawa; Kenichi Agawa; Hiroyuki Shibayama; Ryota Terauchi; Katsumi Hisano; Hiroki Ishikuro; Shouhei Kousai; Hiroyuki Kobayashi; Hideaki Majima; Toru Takayama; Masayuki Koizumi; Fumitoshi Hatori (IEICE Trans. Electron., 2005)

A novel quality factor tuning scheme for active-RC filters. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (ESSCIRC, 2007)

A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (IEEE J. Solid State Circuits, 2007)

A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier. - Shouhei Kousai; Daisuke Miyashita; Junji Wadatsumi; Asuka Maki; Takahiro Sekiguchi; Rui Ito; Mototsugu Hamada (ISSCC, 2008)

A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter. - Shouhei Kousai; Mototsugu Hamada; Rui Ito; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement. - Shouhei Kousai; Ali Hajimiri (IEEE J. Solid State Circuits, 2009)

An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS. - Hiroyuki Kobayashi; Shouhei Kousai; Yoshiaki Yoshihara; Mototsugu Hamada (ISSCC, 2011)

A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio. - Shouhei Kousai; Daisuke Miyashita; Junji Wadatsumi; Rui Ito; Takahiro Sekiguchi; Mototsugu Hamada; Kenichi Okada 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (ISSCC, 2012)

Session 9 overview: Wireless transceiver techniques: Wireless subcommittee. - Sven Mattisson; Shouhei Kousai (ISSCC, 2012)

A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter. - Daisuke Miyashita; Hiroyuki Kobayashi; Jun Deguchi; Shouhei Kousai; Mototsugu Hamada; Ryuichi Fujimoto (IEICE Trans. Electron., 2012)

A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (IEEE J. Solid State Circuits, 2012)

A fully differential ultra-compact broadband transformer based quadrature generation scheme. - Jong Seok Park 001; Shouhei Kousai; Hua Wang 006 (CICC, 2013)

A supply-noise-rejection technique in ADPLL with noise-cancelling current source. - Yusuke Niki; Daisuke Miyashita; Hiroyuki Kobayashi; Shouhei Kousai (ESSCIRC, 2013)

A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC. - Jun Deguchi; Fumihiko Tachibana; Makoto Morimoto; Masayoshi Chiba; Takeshi Miyaba; Hideki Tanaka; Kyoichi Takenaka; Satoshi Funayama; Kunihiko Amano; Kazuhide Sugiura; Ryuta Okamoto; Shouhei Kousai (ISSCC, 2013)

Session 25 overview: Energy-efficient wireless. - Shouhei Kousai; Gangadhar Burra (ISSCC, 2013)

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. - Daisuke Miyashita; Ryo Yamaki; Kazunori Hashiyoshi; Hiroyuki Kobayashi; Shouhei Kousai; Yukihito Oowaki; Yasuo Unekawa (ISSCC, 2013)

A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication. - Jun Deguchi; Toshiyuki Yamagishi; Hideaki Majima; Nau Ozaki; Kazuhiro Hiwada; Makoto Morimoto; Tatsuji Ashitani; Shouhei Kousai (A-SSCC, 2014)

A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations. - Shouhei Kousai; Kohei Onizuka; Song Hu 003; Hua Wang 006; Ali Hajimiri (CICC, 2014)

3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (ISSCC, 2014)

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. - Konosuke Watanabe; Kenichiro Yoshii; Nobuhiro Kondo; Ken-ichi Maeda; Toshio Fujisawa; Junji Wadatsumi; Daisuke Miyashita; Shouhei Kousai; Yasuo Unekawa; Shinsuke Fujii; Takuma Aoyama; Takayuki Tamura; et al. (ISSCC, 2014)

A 2.9mW, +/- 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration. - Yuji Satoh; Hiroyuki Kobayashi; Takeshi Miyaba; Shouhei Kousai (VLSIC, 2014)

Recent progress in CMOS RF circuit design. - Shouhei Kousai (IEICE Electron. Express, 2014)

Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier. - Shouhei Kousai; Kohei Onizuka; Junji Wadatsumi; Takashi Yamaguchi; Yasuhiko Kuriyama; Masami Nagaoka (IEEE J. Solid State Circuits, 2014)

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing. - Daisuke Miyashita; Ryo Yamaki; Kazunori Hashiyoshi; Hiroyuki Kobayashi; Shouhei Kousai; Yukihito Oowaki; Yasuo Unekawa (IEEE J. Solid State Circuits, 2014)

2.8 A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement. - Song Hu 003; Shouhei Kousai; Hua Wang 006 (ISSCC, 2015)

F5: Advanced RF CMOS transmitter techniques. - Piet Wambacq; Stefano Pellerano; Sven Mattisson; Shouhei Kousai; Ali Afsahi; Taizo Yamawaki (ISSCC, 2015)

Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS. - Song Hu 003; Shouhei Kousai; Jong Seok Park 001; Outmane Lemtiri Chlieh; Hua Wang 006 (IEEE J. Solid State Circuits, 2015)

Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology. - Daisuke Miyashita; Shouhei Kousai; Tomoya Suzuki; Jun Deguchi (A-SSCC, 2016)

A Broadband Mixed-Signal CMOS Power Amplifier With a Hybrid Class-G Doherty Efficiency Enhancement Technique. - Song Hu 003; Shouhei Kousai; Hua Wang 006 (IEEE J. Solid State Circuits, 2016)

A Compact Broadband Mixed-Signal Power Amplifier in Bulk CMOS With Hybrid Class-G and Dynamic Load Trajectory Manipulation. - Song Hu 003; Shouhei Kousai; Hua Wang 006 (IEEE J. Solid State Circuits, 2017)

A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing. - Daisuke Miyashita; Shouhei Kousai; Tomoya Suzuki; Jun Deguchi (IEEE J. Solid State Circuits, 2017)