The Microarchitecture of the CUE-v2 Processor: Enabling the Simultaneous Processing of Dataflow and Control-Flow Threads. - Shinya Ito; Shouhei Nomoto; Hiroshi Tomiyasu; Hiroaki Nishikawa (PDPTA, 2004)

A low-cost mixed-mode parallel processor architecture for embedded systems. - Shorin Kyo; Takuya Koga; Hanno Lieske; Shouhei Nomoto; Shin'ichiro Okazaki (ICS, 2007)

IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems. - Shorin Kyo; Shouhei Nomoto; Takuya Koga; Hanno Lieske; Shin'ichiro Okazaki (Hot Chips Symposium, 2009)

Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors. - Shorin Kyo; Shouhei Nomoto; Shin'ichiro Okazaki (ICDSC, 2009)

Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application. - Shouhei Nomoto; Shorin Kyo; Shin'ichiro Okazaki (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems. - Shouhei Nomoto; Shorin Kyo; Shin'ichiro Okazaki (A-SSCC, 2011)

Efficient data transfer operations for a SIMD processor array system. - Hanno Lieske; Shorin Kyo; Shouhei Nomoto; Sunao Torii; Yuki Kobayashi; Yasuyuki Ninomiya; Shin'ichiro Okazaki (ICASSP, 2012)