A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip. - Narendra Kumar Meena; Hemangee K. Kapoor; Shounak Chakraborty 001 (VDAT, 2014)

Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. - Shounak Chakraborty 001; Shirshendu Das; Hemangee K. Kapoor (IPDPS Workshops, 2015)

Static energy reduction by performance linked cache capacity management in tiled CMPs. - Hemangee K. Kapoor; Shirshendu Das; Shounak Chakraborty 001 (SAC, 2015)

Power aware cache miss reduction by energy efficient victim retention. - Shounak Chakraborty 001; Shirshendu Das; Hemangee K. Kapoor (VDAT, 2015)

Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. - Shounak Chakraborty 001; Shirshendu Das; Hemangee K. Kapoor (SAC, 2016)

Static energy reduction by performance linked dynamic cache resizing. - Shounak Chakraborty 001; Hemangee K. Kapoor (VLSI-SoC, 2016)

Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors. - Shounak Chakraborty 001; Hemangee K. Kapoor (VLSID, 2017)

Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs. - Shounak Chakraborty 001; Hemangee K. Kapoor (Microprocess. Microsystems, 2017)

Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors. - Ashwini A. Kulkarni; Shounak Chakraborty 001; Shrinivas P. Mahajan; Hemangee K. Kapoor (ACM Great Lakes Symposium on VLSI, 2018)

Analysing the Role of Last Level Caches in Controlling Chip Temperature. - Shounak Chakraborty 001; Hemangee K. Kapoor (IEEE Trans. Sustain. Comput., 2018)

Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design. - Shounak Chakraborty 001; Hemangee K. Kapoor (ACM Trans. Design Autom. Electr. Syst., 2019)

RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress. - Shounak Chakraborty 001; Sangeet Saha; Magnus Själander; Klaus D. McDonald-Maier (CODES+ISSS, 2020)

ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. - Sukarn Agarwal; Shounak Chakraborty 001 (ASAP, 2021)

SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorEReal-time Systems. - Sanjay Moulik; Zinea Das; Rajesh Devaraj; Shounak Chakraborty 001 (J. Syst. Archit., 2021)

WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. - Shounak Chakraborty 001; Magnus Själander (ACM Trans. Archit. Code Optim., 2021)

Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. - Shounak Chakraborty 001; Sangeet Saha; Magnus Själander; Klaus D. McDonald-Maier (ACM Trans. Embed. Comput. Syst., 2021)

STIFF: thermally safe temperature effect inversion aware FinFET based multi-core. - Shounak Chakraborty 001; Vassos Soteriou; Magnus Själander (CF, 2022)

RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore. - Yanshul Sharma; Sanjay Moulik; Shounak Chakraborty 001 (DATE, 2022)

ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches. - Sangeet Saha; Shounak Chakraborty 001; Xiaojun Zhai; Shoaib Ehsan; Klaus D. McDonald-Maier (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms. - Yanshul Sharma; Shounak Chakraborty 001; Sanjay Moulik (J. Supercomput., 2022)

Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). - Sukarn Agarwal; Shounak Chakraborty 001; Magnus Själander (DAC, 2023)

NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems. - Shounak Chakraborty 001; Mehdi Safarpour; Olli Silvén (SAMOS, 2023)

DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. - Sangeet Saha; Shounak Chakraborty 001; Sukarn Agarwal; Rahul Gangopadhyay; Magnus Själander; Klaus D. McDonald-Maier (IEEE Trans. Parallel Distributed Syst., 2023)

MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. - Shounak Chakraborty 001; Sangeet Saha; Magnus Själander; Klaus D. McDonald-Maier (DAC, 2024)

TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. - Sukarn Agarwal; Shounak Chakraborty 001; Magnus Själander (IPDPS, 2024)

TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores. - Shounak Chakraborty 001; Yanshul Sharma; Sanjay Moulik (ACM Trans. Embed. Comput. Syst., 2024)

ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. - Sangeet Saha; Shounak Chakraborty 001; Sukarn Agarwal; Magnus Själander; Klaus D. McDonald-Maier (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM-Based Caches. - Shounak Chakraborty 001; Thanasin Bunnam; Jedsada Arunruerk; Sukarn Agarwal; Shengqi Yu; Rishad A. Shafik; Magnus Själander (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)