A systolic array implementation of common factor algorithm to compute DFT. - Shousheng He; Mats Torkelson (ISPAN, 1994)

A Pipelined Bit-Serial Complex Multiplier Using Distributed Arithmetic. - Shousheng He; Mats Torkelson (ISCAS, 1995)

VLSI computation of the partial DFT for (de)modulation in multi-channel OFDM system. - Shousheng He; Mats Torkelson (PIMRC, 1995)

A New Approach to Pipeline FFT Processor. - Shousheng He; Mats Torkelson (IPPS, 1996)

Computing partial DFT for comb spectrum evaluation. - Shousheng He; Mats Torkelson (IEEE Signal Process. Lett., 1996)

Design and implementation of a 1024-point pipeline FFT processor. - Shousheng He; Mats Torkelson (CICC, 1998)

An Orthogonal Time-Frequency Extraction Approach to 2D Systolic Architecture for 1D DFT Computation. - Shousheng He; Mats Torkelson (J. VLSI Signal Process., 1999)