Multipath minimum energy routing in ad hoc network. - Shouyi Yin; Xiaokang Lin (ICC, 2005)

Multipath Energy Efficient Routing in Mobile Ad Hoc Network. - Shouyi Yin; Xiaokang Lin (ICN (2), 2005)

Adaptive load balancing in mobile ad hoc networks. - Shouyi Yin; Xiaokang Lin (WCNC, 2005)

Prediction-based routing for real time communications in wireless multi-hop networks. - Shouyi Yin; Yongqiang Xiong; Qian Zhang 001; Xiaokang Lin (QSHINE, 2006)

Traffic-aware routing for real-time communications in wireless multi-hop networks. - Shouyi Yin; Yongqiang Xiong; Qian Zhang 001; Xiaokang Lin (Wirel. Commun. Mob. Comput., 2006)

Buffer planning for application-specific networks-on-chip design. - Shouyi Yin; Leibo Liu; Shaojun Wei (Sci. China Ser. F Inf. Sci., 2009)

Compiler Framework for Reconfigurable Computing Architecture. - Chongyong Yin; Shouyi Yin; Leibo Liu; Shaojun Wei (IEICE Trans. Electron., 2009)

Mixed-level modeling for network on chip infrastructure in SoC design. - Yang Hu 001; Shouyi Yin; Leibo Liu; Shaojun Wei (APCCAS, 2010)

Battery aware tasks allocating algorithm for multi-battery operated system. - Peng Ouyang; Shouyi Yin; Leibo Liu; Shaojun Wei (APCCAS, 2010)

Syndrome differentiation of fatty liver based on the whole network analysis theory. - Shouyi Yin; Tao Liu; Huafeng Wei; Guang Ji (BIBM Workshops, 2010)

Parallel implementation of computing-intensive decoding algorithms of H.264 on reconfigurable SoC. - Tongsheng Geng; Leibo Liu; Shouyi Yin; Min Zhu 001; Wen Jia; Shaojun Wei (ISCAS, 2010)

A VLSI design of sensor node for wireless image sensor network. - Renyan Zhou; Leibo Liu; Shouyi Yin; Ao Luo; Xinkai Chen; Shaojun Wei (ISCAS, 2010)

A reconfigurable multi-processor SoC for media applications. - Min Zhu 001; Leibo Liu; Shouyi Yin; Yansheng Wang; Wenjie Wang; Shaojun Wei (ISCAS, 2010)

Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System. - Tongsheng Geng; Leibo Liu; Shouyi Yin; Min Zhu 001; Shaojun Wei (IEICE Trans. Inf. Syst., 2010)

CropNET: A Wireless Multimedia Sensor Network for Agricultural Monitoring. - Shouyi Yin; Zhongfu Sun; Leibo Liu; Shaojun Wei (IEICE Trans. Commun., 2010)

A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System. - Min Zhu 001; Leibo Liu; Shouyi Yin; Chongyong Yin; Shaojun Wei (IEICE Trans. Inf. Syst., 2010)

Performance evaluation modeling for reconfigurable processor. - Shuang Liang 012; Shouyi Yin; Chongyong Yin; Leibo Liu; Shaojun Wei (ASICON, 2011)

A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems. - Shouyi Yin; Jianwei Cui; Ao Luo; Leibo Liu; Shaojun Wei (ASICON, 2011)

Reducing configuration contexts for coarse-grained reconfigurable architecture. - Shouyi Yin; Chongyong Yin; Leibo Liu; Min Zhu 001; Yansheng Wang; Shaojun Wei (ISCAS, 2012)

Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture. - Dajiang Liu; Shouyi Yin; Chongyong Yin; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2012)

Multi-Battery Scheduling for Battery-Powered DVS Systems. - Peng Ouyang; Shouyi Yin; Leibo Liu; Shaojun Wei (IEICE Trans. Commun., 2012)

Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC. - Shouyi Yin; Yang Hu 001; Zhen Zhang; Leibo Liu; Shaojun Wei (IEICE Trans. Electron., 2012)

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture. - Shouyi Yin; Chongyong Yin; Leibo Liu; Min Zhu 001; Shaojun Wei (IEICE Trans. Inf. Syst., 2012)

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. - Leibo Liu; Chenchen Deng; Dong Wang 040; Min Zhu 001; Shouyi Yin; Peng Cao 002; Shaojun Wei (CICC, 2013)

SURFEX: A 57fps 1080P resolution 220mW silicon implementation for simplified speeded-up robust feature with 65nm process. - Leibo Liu; Weilong Zhang; Chenchen Deng; Shouyi Yin; Shanshan Cai; Shaojun Wei (CICC, 2013)

Polyhedral model based mapping optimization of loop nests for CGRAs. - Dajiang Liu; Shouyi Yin; Leibo Liu; Shaojun Wei (DAC, 2013)

Mapping IDCT of MPEG2 on Coarse-Grained Reconfigurable Array for Matching 1080p Video Decoding. - Guoyong Li; Leibo Liu; Shouyi Yin; Changkui Mao; Shaojun Wei (EMC/HumanCom, 2013)

Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor. - Leibo Liu; Yingjie Victor Chen; Shouyi Yin; Dong Wang 040; Xing Wang; Shaojun Wei; Li Zhou 015; Hao Lei; Peng Cao 002 (ISCAS, 2013)

Affine transformations for communication and reconfiguration optimization of loops on CGRAs. - Dajiang Liu; Shouyi Yin; Leibo Liu; Shaojun Wei (ISCAS, 2013)

A VLSI architecture for enhancing the fault tolerance of NoC using quad-spare mesh topology and dynamic reconfiguration. - Yu Ren; Leibo Liu; Shouyi Yin; Qinghua Wu; Shaojun Wei; Jie Han 001 (ISCAS, 2013)

Battery-Aware MAC Analytical Modeling for Extending Lifetime of Low Duty-Cycled Wireless Sensor Network. - Yulin Li; Shouyi Yin; Leibo Liu; Shaojun Wei; Dong Wang 040 (NAS, 2013)

SPC: An Approach to Guarantee Performance in Cost Oriented Mapping Algorithm for NoC Architectures. - Qinghua Wu; Leibo Liu; Shouyi Yin; Yu Ren; Shaojun Wei (NAS, 2013)

ReSSIM: a mixed-level simulator for dynamic coarse-grained reconfigurable processor. - Leibo Liu; Wen Jia; Shouyi Yin; Dong Wang 040; Guanyi Sun; Eugene Tang; Shaojun Wei (Sci. China Inf. Sci., 2013)

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (Sci. China Inf. Sci., 2013)

An efficient VLSI architecture of speeded-up robust feature extraction for high resolution and high frame rate video. - Weilong Zhang; Leibo Liu; Shouyi Yin; Renyan Zhou; Shanshan Cai; Shaojun Wei (Sci. China Inf. Sci., 2013)

Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System. - Peng Ouyang; Shouyi Yin; Hui Gao; Leibo Liu; Shaojun Wei (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs. - Shouyi Yin; Dajiang Liu; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2013)

Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture. - Shouyi Yin; Rui Shi; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2013)

An Inductive-Coupling Interconnected Application-Specific 3D NoC Design. - Zhen Zhang; Shouyi Yin; Leibo Liu; Shaojun Wei (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features. - Jienan Zhang; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Calibration Techniques for Low-Power Wireless Multiband Transceiver. - Shouyi Yin; Jianwei Cui; Leibo Liu; Shaojun Wei (Int. J. Distributed Sens. Networks, 2013)

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration. - Yu Ren; Leibo Liu; Shouyi Yin; Jie Han 001; Qinghua Wu; Shaojun Wei (J. Syst. Archit., 2013)

A High Precision Feature Based on LBP and Gabor Theory for Face Recognition. - Wei Xia; Shouyi Yin; Peng Ouyang (Sensors, 2013)

Low-Power Reconfigurable Processor Utilizing Variable Dual VDD. - Jianfeng Zhu 001; Leibo Liu; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms. - Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (DATE, 2014)

Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures. - Dajiang Liu; Shouyi Yin; Leibo Liu; Shaojun Wei (FCCM, 2014)

Teach Reconfigurable Computing using mixed-grained fabrics based hardware infrastructure. - Chenchen Deng; Leibo Liu; Zhaoshi Li; Shouyi Yin; Shaojun Wei (FIE, 2014)

Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. - Chen Yang 005; Leibo Liu; Yansheng Wang; Shouyi Yin; Peng Cao 002; Shaojun Wei (FPL, 2014)

A FAST Extreme Illumination Robust Feature in Affine Space. - Peng Ouyang; Shouyi Yin; Leibo Liu; Shaojun Wei (ICPR, 2014)

Map-reduce inspired loop parallelization on CGRA. - Shengjia Shao; Shouyi Yin; Leibo Liu; Shaojun Wei (ISCAS, 2014)

A parallel hardware architecture for fast integral image computing. - Yuchi Zhang; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (ISCAS, 2014)

A 65 nm uneven-dual-core SoC based platform for multi-device collaborative computing. - Wenping Zhu; Leibo Liu; Shouyi Yin; Yuan Dong; Shaojun Wei; Eugene Y. Tang; Jiqiang Song; Jinzhan Peng (ISCAS, 2014)

Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD. - Bing Xu 001; Shouyi Yin; Leibo Liu; Shaojun Wei (MWSCAS, 2014)

A fast and robust traffic sign recognition method using ring of RIBP histograms based feature. - Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (ROBIO, 2014)

Optimization of speeded-up robust feature algorithm for hardware implementation. - Shanshan Cai; Leibo Liu; Shouyi Yin; Renyan Zhou; Weilong Zhang; Shaojun Wei (Sci. China Inf. Sci., 2014)

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor. - Leibo Liu; Yingjie Victor Chen; Dong Wang 040; Shouyi Yin; Xing Wang; Long Wang; Hao Lei; Peng Cao 002; Shaojun Wei (Sci. China Inf. Sci., 2014)

Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system. - Leibo Liu; Yingjie Victor Chen; Shouyi Yin; Li Zhou 015; Hang Yuan; Shaojun Wei (Sci. China Inf. Sci., 2014)

Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture. - Leibo Liu; Yansheng Wang; Shouyi Yin; Min Zhu 001; Xing Wang; Shaojun Wei (Sci. China Inf. Sci., 2014)

MapReduce inspired loop mapping for coarse-grained reconfigurable architecture. - Shouyi Yin; Shengjia Shao; Leibo Liu; Shaojun Wei (Sci. China Inf. Sci., 2014)

A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision. - Ruoyu Xu; Wai Chiu Ng; George Jie Yuan; Shouyi Yin; Shaojun Wei (IEEE J. Solid State Circuits, 2014)

A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps. - Shouyi Yin; Xu Dai; Peng Ouyang; Leibo Liu; Shaojun Wei (Sensors, 2014)

An uneven-dual-core processor based mobile platform for facilitating the collaboration among various embedded electronic devices. - Leibo Liu; Wenping Zhu; Shouyi Yin; Eugene Tang; Paul Peng (IEEE Trans. Consumer Electron., 2014)

SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration. - Leibo Liu; Dong Wang 040; Shouyi Yin; Yingjie Victor Chen; Min Zhu 001; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures. - Leibo Liu; Yu Ren; Chenchen Deng; Shouyi Yin; Shaojun Wei; Jie Han 001 (ASP-DAC, 2015)

Battery-aware mapping optimization of loop nests for CGRAs. - Yu Peng; Shouyi Yin; Leibo Liu; Shaojun Wei (ASP-DAC, 2015)

A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space. - Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (CICC, 2015)

A 127 fps in full hd accelerator based on optimized AKAZE with efficiency and effectiveness for image feature extraction. - Guangli Jiang; Leibo Liu; Wenping Zhu; Shouyi Yin; Shaojun Wei (DAC, 2015)

Efficient memory partitioning for parallel data access in multidimensional arrays. - Chenyue Meng; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (DAC, 2015)

Acceleration of control flows on reconfigurable architecture with a composite method. - Junbin Wang; Leibo Liu; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei (DAC, 2015)

RNA: a reconfigurable architecture for hardware neural acceleration. - Fengbin Tu; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (DATE, 2015)

Joint affine transformation and loop pipelining for mapping nested loop on CGRAs. - Shouyi Yin; Dajiang Liu; Leibo Liu; Shaojun Wei; Yike Guo (DATE, 2015)

Cooperatively managing dynamic writeback and insertion policies in a last-level DRAM cache. - Shouyi Yin; Jiakun Li; Leibo Liu; Shaojun Wei; Yike Guo (DATE, 2015)

A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only). - Leibo Liu; Yingjie Victor Chen; Dong Wang 040; Min Zhu 001; Shouyi Yin; Shaojun Wei (FPGA, 2015)

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only). - Junbin Wang; Leibo Liu; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei (FPGA, 2015)

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only). - Chen Yang 005; Leibo Liu; Shouyi Yin; Shaojun Wei (FPGA, 2015)

Acceleration of Nested Conditionals on CGRAs via Trigger Scheme. - Shouyi Yin; Pengcheng Zhou; Leibo Liu; Shaojun Wei (ICCAD, 2015)

An automatic depth map generation method by image classification. - Hao Dong; Shouyi Yin; Guangli Jiang; Leibo Liu; Shaojun Wei (ICCE, 2015)

Efficient lane detection system based on monocular camera. - Tao Tan; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (ICCE, 2015)

Real-time time-consistent 2D-to-3D video conversion based on color histogram. - Zhen Zhang; Shouyi Yin; Leibo Liu; Shaojun Wei (ICCE, 2015)

Neural approximating architecture targeting multiple application domains. - Fengbin Tu; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (ISCAS, 2015)

A Multi-modal 2D + 3D Face Recognition Method with a Novel Local Feature Descriptor. - Xu Dai; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (WACV, 2015)

Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints. - Chen Wu; Chenchen Deng; Leibo Liu; Shouyi Yin; Jie Han 001; Shaojun Wei (Sci. China Inf. Sci., 2015)

Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral Optimizations. - Dajiang Liu; Shouyi Yin; Leibo Liu; Shaojun Wei (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Battery-Aware Loop Nests Mapping for CGRAs. - Yu Peng; Shouyi Yin; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2015)

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture. - Rui Shi; Shouyi Yin; Leibo Liu; Qiongbing Liu; Shuang Liang 012; Shaojun Wei (IEICE Trans. Inf. Syst., 2015)

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD. - Bing Xu 001; Shouyi Yin; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2015)

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array. - Chen Yang 005; Leibo Liu; Yansheng Wang; Shouyi Yin; Peng Cao 002; Shaojun Wei (J. Circuits Syst. Comput., 2015)

A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction. - Guangli Jiang; Leibo Liu; Wenping Zhu; Shouyi Yin; Shaojun Wei (Sensors, 2015)

High-Performance Motion Estimation for Image Sensors with Video Compression. - Weizhi Xu 001; Shouyi Yin; Leibo Liu; Zhiyong Liu 002; Shaojun Wei (Sensors, 2015)

A Novel 2D-to-3D Video Conversion Method Using Time-Coherent Depth Maps. - Shouyi Yin; Hao Dong; Guangli Jiang; Leibo Liu; Shaojun Wei (Sensors, 2015)

Fast Traffic Sign Recognition with a Rotation Invariant Binary Pattern Based Feature. - Shouyi Yin; Peng Ouyang; Leibo Liu; Yike Guo; Shaojun Wei (Sensors, 2015)

An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures. - Chen Wu; Chenchen Deng; Leibo Liu; Jie Han 001; Jiqiang Chen; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency. - Peng Ouyang; Shouyi Yin; Yuchi Zhang; Leibo Liu; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A real-time time-consistent 2D-to-3D video conversion system using color histogram. - Zhen Zhang; Shouyi Yin; Leibo Liu; Shaojun Wei (IEEE Trans. Consumer Electron., 2015)

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm. - Yu Ren; Leibo Liu; Shouyi Yin; Jie Han 001; Shaojun Wei (ACM Trans. Reconfigurable Technol. Syst., 2015)

A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures. - Leibo Liu; Chen Wu; Chenchen Deng; Shouyi Yin; Qinghua Wu; Jie Han 001; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures. - Dajiang Liu; Shouyi Yin; Yu Peng; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms. - Peng Ouyang; Shouyi Yin; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels. - Jianfeng Zhu 001; Leibo Liu; Shouyi Yin; Xiao Yang; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. - Xinhan Lin; Shouyi Yin; Leibo Liu; Shaojun Wei (ASP-DAC, 2016)

Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays. - Chen Yang 005; Leibo Liu; Shouyi Yin; Shaojun Wei (DAC, 2016)

Multibank memory optimization for parallel data access in multiple data arrays. - Shouyi Yin; Zhicong Xie; Chenyue Meng; Leibo Liu; Shaojun Wei (ICCAD, 2016)

Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. - Shouyi Yin; Xianqing Yao; Tianyi Lu; Leibo Liu; Shaojun Wei (ICCAD, 2016)

Energy management on DVS based coarse-grained reconfigurable platform. - Peng Ouyang; Shouyi Yin; Chunxiao Xing; Leibo Liu; Shaojun Wei (NANOARCH, 2016)

A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. - Shuang Liang 012; Shouyi Yin; Leibo Liu; Yike Guo; Shaojun Wei (IEEE Comput. Archit. Lett., 2016)

A fast face detection architecture for auto-focus in smart-phones and digital cameras. - Peng Ouyang; Shouyi Yin; Chenchen Deng; Leibo Liu; Shaojun Wei (Sci. China Inf. Sci., 2016)

An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform. - Leibo Liu; Dong Wang 040; Yingjie Chen; Min Zhu 001; Shouyi Yin; Shaojun Wei (IEICE Trans. Inf. Syst., 2016)

Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. - Shouyi Yin; Jiangyuan Gu; Dajiang Liu; Leibo Liu; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation. - Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator. - Wenping Zhu; Leibo Liu; Guangli Jiang; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. Video Technol., 2016)

Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture. - Bo Wang 023; Leibo Liu; Chenchen Deng; Min Zhu 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Inf. Forensics Secur., 2016)

TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions. - Leibo Liu; Junbin Wang; Jianfeng Zhu 001; Chenchen Deng; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2016)

Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures. - Shouyi Yin; Xinhan Lin; Leibo Liu; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2016)

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. - Shouyi Yin; Dajiang Liu; Yu Peng; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing. - Shouyi Yin; Peng Ouyang; Tianbao Chen; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2016)

CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache. - Shouyi Yin; Weizhi Xu 001; Jiakun Li; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. - Shouyi Yin; Xianqing Yao; Dajiang Liu; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Trigger-Centric Loop Mapping on CGRAs. - Shouyi Yin; Pengcheng Zhou; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. - Jiangyuan Gu; Shouyi Yin; Leibo Liu; Shaojun Wei (ASP-DAC, 2017)

Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. - Jiangyuan Gu; Shouyi Yin; Shaojun Wei (DAC, 2017)

A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications. - Peng Ouyang; Shouyi Yin; Shaojun Wei (DAC, 2017)

Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. - Shouyi Yin; Zhicong Xie; Shaojun Wei (DAC, 2017)

Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. - Jianxin Guo; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (FCCM, 2017)

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). - Tianyi Lu; Shouyi Yin; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (FPGA, 2017)

Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). - Shouyi Yin; Dajiang Liu; Lifeng Sun; Xinhan Lin; Leibo Liu; Shaojun Wei (FPGA, 2017)

A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation. - Peng Ouyang; Shouyi Yin; Chunxiao Xing; Leibo Liu; Shaojun Wei (ACM Great Lakes Symposium on VLSI, 2017)

Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. - Zhaoshi Li; Leibo Liu; Yangdong Deng; Shouyi Yin; Yao Wang; Shaojun Wei (ISCA, 2017)

Memory fartitioning-based modulo scheduling for high-level synthesis. - Tianyi Lu; Shouyi Yin; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (ISCAS, 2017)

DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach. - Shouyi Yin; Dajiang Liu; Lifeng Sun; Leibo Liu; Shaojun Wei (ISCAS, 2017)

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs. - Shibin Tang; Shouyi Yin; Shixuan Zheng; Peng Ouyang; Fengbin Tu; Leiyue Yao; JinZhou Wu; Wenming Cheng; Leibo Liu; Shaojun Wei (NVMSA, 2017)

Multi-CNN and decision tree based driving behavior evaluation. - Shouyi Yin; Jinjin Duan; Peng Ouyang; Leibo Liu; Shaojun Wei (SAC, 2017)

Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion. - Weizhi Xu 001; Shouyi Yin; Zhen Zhang; Hao Dong; Rui Shi; Leibo Liu; Shaojun Wei (IEEE Access, 2017)

Implementation of in-loop filter for HEVC decoder on reconfigurable processor. - Leibo Liu; Yingjie Chen; Chenchen Deng; Shouyi Yin; Shaojun Wei (IET Image Process., 2017)

An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation. - Shouyi Yin; Peng Ouyang; Xu Dai; Leibo Liu; Shaojun Wei (IEEE Syst. J., 2017)

PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC. - Chenchen Deng; Leibo Liu; Yang Liu 326; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks. - Bo Wang 023; Leibo Liu; Chenchen Deng; Min Zhu 001; Shouyi Yin; Zhuoquan Zhou; Shaojun Wei (IEEE Trans. Inf. Forensics Secur., 2017)

A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems. - Chen Wu; Chenchen Deng; Leibo Liu; Jie Han 001; Jiqiang Chen; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2017)

CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. - Chen Yang 005; Leibo Liu; Kai Luo; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2017)

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. - Shouyi Yin; Xianqing Yao; Tianyi Lu; Dajiang Liu; Jiangyuan Gu; Leibo Liu; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2017)

Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture. - Guiqiang Peng; Leibo Liu; Peng Zhang; Shouyi Yin; Shaojun Wei (IEEE Trans. Signal Process., 2017)

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. - Fengbin Tu; Shouyi Yin; Peng Ouyang; Shibin Tang; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 4K×2K@60fps Multi-format Multi-function Display Processor for High Perceptual Quality. - Hang Wang; Hongbin Sun 001; Xuchong Zhang; Qiubo Chen; Pengju Ren; Xiaogang Wu; Shouyi Yin; Zhiqiang Jiang; Xiang Li; Daqiang Han; Shiquan Yu; Shaojun Wei; et al. (APCCAS, 2018)

A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems. - Guiqiang Peng; Leibo Liu; Qiushi Wei; Yao Wang; Shouyi Yin; Shaojun Wei (A-SSCC, 2018)

A Full Multicast Reconfigurable Non-blocking Permutation Network. - Hang Yuan; Leibo Liu; Hui Li; Shouyi Yin; Shaojun Wei (CyberC, 2018)

LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. - Xinhan Lin; Shouyi Yin; Fengbin Tu; Leibo Liu; Xiangyu Li; Shaojun Wei (DAC, 2018)

An efficient kernel transformation architecture for binary- and ternary-weight neural network inference. - Shixuan Zheng; Yonggang Liu; Shouyi Yin; Leibo Liu; Shaojun Wei (DAC, 2018)

Efficient Hardware Architecture of Softmax Layer in Deep Neural Network. - Ruofei Hu; Binren Tian; Shouyi Yin; Shaojun Wei (DSP, 2018)

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. - Fengbin Tu; Weiwei Wu; Shouyi Yin; Leibo Liu; Shaojun Wei (ISCA, 2018)

Bit-width Adaptive Accelerator Design for Convolution Neural Network. - Jianxin Guo; Shouyi Yin; Peng Ouyang; Fengbin Tu; Shibin Tang; Leibo Liu; Shaojun Wei (ISCAS, 2018)

An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. - Zhihui Wang; Shouyi Yin; Fengbin Tu; Leibo Liu; Shaojun Wei (ISCAS, 2018)

An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS. - Shouyi Yin; Peng Ouyang; Jianxun Yang; Tianyi Lu; Xiudong Li; Leibo Liu; Shaojun Wei (VLSI Circuits, 2018)

A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS. - Shouyi Yin; Peng Ouyang; Shixuan Zheng; Dandan Song; Xiudong Li; Leibo Liu; Shaojun Wei (VLSI Circuits, 2018)

Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. - Shouyi Yin; Tianyi Lu; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (IEEE Access, 2018)

Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution. - Zhaoshi Li; Leibo Liu; Yangdong Deng; Shouyi Yin; Shaojun Wei (IEEE Comput. Archit. Lett., 2018)

FP-BNN: Binarized neural network on FPGA. - Shuang Liang 012; Shouyi Yin; Leibo Liu; Wayne Luk; Shaojun Wei (Neurocomputing, 2018)

Optimization of Softmax Layer in Deep Neural Network Using Integral Stochastic Computation. - Ruofei Hu; Binren Tian; Shouyi Yin; Shaojun Wei (J. Low Power Electron., 2018)

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. - Shouyi Yin; Peng Ouyang; Shibin Tang; Fengbin Tu; Xiudong Li; Shixuan Zheng; Tianyi Lu; Jiangyuan Gu; Leibo Liu; Shaojun Wei (IEEE J. Solid State Circuits, 2018)

Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms. - Leibo Liu; Bo Wang 023; Chenchen Deng; Min Zhu 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. - Leibo Liu; Chen Yang 005; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. - Leibo Liu; Zhuoquan Zhou; Shaojun Wei; Min Zhu 001; Shouyi Yin; Shengyang Mao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration. - Jiale Yan; Shouyi Yin; Fengbin Tu; Leibo Liu; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. - Shouyi Yin; Zhicong Xie; Chenyue Meng; Peng Ouyang; Leibo Liu; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. - Leibo Liu; Zhaoshi Li; Chen Yang 005; Chenchen Deng; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT. - Peng Ouyang; Shouyi Yin; Leibo Liu; Youguang Zhang; Weisheng Zhao; Shaojun Wei (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128 times 8 64$ -QAM Massive MIMO in 65 nm CMOS. - Guiqiang Peng; Leibo Liu; Sheng Zhou 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration. - Jiangyuan Gu; Shouyi Yin; Leibo Liu; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2018)

Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays. - Yanan Lu; Leibo Liu; Yangdong Deng; Jian Weng 004; Shouyi Yin; Yiyu Shi 001; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2018)

Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems. - Guiqiang Peng; Leibo Liu; Sheng Zhou 001; Yang Xue; Shouyi Yin; Shaojun Wei (IEEE Trans. Signal Process., 2018)

Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. - Shouyi Yin; Tianyi Lu; Zhicong Xie; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Small-Footprint Keyword Spotting with Graph Convolutional Network. - Xi Chen; Shouyi Yin; Dandan Song; Peng Ouyang; Leibo Liu; Shaojun Wei (ASRU, 2019)

Constructing Concurrent Data Structures on FPGA with Channels. - Hui Yan; Zhaoshi Li; Leibo Liu; Shouyi Yin; Shaojun Wei (FPGA, 2019)

A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network. - Yu Pan; Peng Ouyang; Yinglin Zhao; Shouyi Yin; Youguang Zhang; Shaojun Wei; Weisheng Zhao (ACM Great Lakes Symposium on VLSI, 2019)

Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor. - Leibo Liu; Ao Luo; Guanhua Li; Jianfeng Zhu 001; Yong Wang; Gang Shan; Jianfeng Pan; Shouyi Yin; Shaojun Wei (Hot Chips Symposium, 2019)

ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms. - Kai Lu; Zhaoshi Li; Leibo Liu; Jiawei Wang; Shouyi Yin; Shaojun Wei (ICCAD, 2019)

A Reliable Physical Unclonable Function Based on Differential Charging Capacitors. - Hang Yuan; Wei Guo 018; Chip-Hong Chang; Yuan Cao 003; Shaojun Wei; Shouyi Yin; Chenchen Deng; Leibo Liu; Wei Ge; Fan Zhang 044 (ISCAS, 2019)

Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation. - Jun Yang 006; Yuyao Kong; Zhen Wang 019; Yan Liu; Bo Wang 023; Shouyi Yin; Longxin Shi (ISSCC, 2019)

Towards Efficient Compact Network Training on Edge-Devices. - Feng Xiong; Fengbin Tu; Shouyi Yin; Shaojun Wei (ISVLSI, 2019)

FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. - Zhaoshi Li; Leibo Liu; Yangdong Deng; Jiawei Wang; Zhiwei Liu; Shouyi Yin; Shaojun Wei (MICRO, 2019)

An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks. - Jianxun Yang; Leibo Liu; Jin Zhang; Shaojun Wei; Shouyi Yin (NANOARCH, 2019)

MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions. - Weiwei Wu; Shouyi Yin; Fengbin Tu; Leibo Liu; Shaojun Wei (NEWCAS, 2019)

A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. - Ruiqi Guo; Yonggang Liu; Shixuan Zheng; Ssu-Yen Wu; Peng Ouyang; Win-San Khwa; Xi Chen; Jia-Jing Chen; Xiudong Li; Leibo Liu; Meng-Fan Chang; Shaojun Wei; et al. (VLSI Circuits, 2019)

THUEE system description for NIST 2019 SRE CTS Challenge. - Yi Liu 049; Tianyu Liang; Can Xu; Xianwei Zhang; Xianhong Chen; Wei-Qiang Zhang 001; Liang He 003; Dandan Song; Ruyun Li; Yangcheng Wu; Peng Ouyang; Shouyi Yin (CoRR, 2019)

An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width. - Shouyi Yin; Peng Ouyang; Jianxun Yang; Tianyi Lu; Xiudong Li; Leibo Liu; Shaojun Wei (IEEE J. Solid State Circuits, 2019)

An STT-MRAM Based in Memory Architecture for Low Power Integral Computing. - Yinglin Zhao; Peng Ouyang; Wang Kang 001; Shouyi Yin; Youguang Zhang; Shaojun Wei; Weisheng Zhao (IEEE Trans. Computers, 2019)

Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack. - Hai Huang; Leibo Liu; Qihuan Huang; Yingjie Chen; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning. - Dajiang Liu; Shouyi Yin; Guojie Luo; Jiaxing Shang; Leibo Liu; Shaojun Wei; Yong Feng 002; Shangbo Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution. - Leibo Liu; Wenping Zhu; Shouyi Yin; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. - Liang Wang 020; Ping Lv; Leibo Liu; Jie Han 001; Ho-fung Leung; Xiaohang Wang 001; Shouyi Yin; Shaojun Wei; Terrence S. T. Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. - Shouyi Yin; Shibin Tang; Xinhan Lin; Peng Ouyang; Fengbin Tu; Leibo Liu; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression. - Man Shi; Peng Ouyang; Shouyi Yin; Leibo Liu; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning. - Shixuan Zheng; Peng Ouyang; Dandan Song; Xiudong Li; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching. - Leibo Liu; Qiang Wang; Wenping Zhu; Huiyu Mo; Tianchen Wang; Shouyi Yin; Yiyu Shi 001; Shaojun Wei (IEEE Trans. Circuits Syst. Video Technol., 2019)

Reconfigurable Architecture for Neural Approximation in Multimedia Computing. - Fengbin Tu; Shouyi Yin; Peng Ouyang; Leibo Liu; Shaojun Wei (IEEE Trans. Circuits Syst. Video Technol., 2019)

Face Alignment With Expression- and Pose-Based Adaptive Initialization. - Huiyu Mo; Leibo Liu; Wenping Zhu; Shouyi Yin; Shaojun Wei (IEEE Trans. Multim., 2019)

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. - Shouyi Yin; Shibin Tang; Xinhan Lin; Peng Ouyang; Fengbin Tu; Leibo Liu; Jishen Zhao; Cong Xu 002; Shuangchen Li; Yuan Xie 001; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2019)

A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. - Jianxun Yang; Yuyao Kong; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Yiqi Wang 005; Yonggang Liu; Chenfu Guo; Te Hu; Congcong Li; Leibo Liu; Jin Zhang; et al. (A-SSCC, 2020)

TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. - Mingyang Kou; Jiangyuan Gu; Shaojun Wei; Hailong Yao; Shouyi Yin (DAC, 2020)

STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. - Feng Xiong; Fengbin Tu; Man Shi; Yang Wang 089; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2020)

A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs. - Ning Li; Leibo Liu; Shaojun Wei; Shouyi Yin (FCCM, 2020)

PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement. - Peishuo Li; Zihang Jiang; Shouyi Yin; Dandan Song; Peng Ouyang; Leibo Liu; Shaojun Wei (ICASSP, 2020)

A Reconfigurable Branch Predictor for Spatial Computing Architectures. - Yanan Lu; Leibo Liu; Jian Liu; Shouyi Yin; Shaojun Wei (ICDSP, 2020)

Transformer with Bidirectional Decoder for Speech Recognition. - Xi Chen; Songyang Zhang; Dandan Song; Peng Ouyang; Shouyi Yin (INTERSPEECH, 2020)

THUEE System for NIST SRE19 CTS Challenge. - Ruyun Li; Tianyu Liang; Dandan Song; Yi Liu 049; Yangcheng Wu; Can Xu; Peng Ouyang; Xianwei Zhang; Xianhong Chen; Weiqiang Zhang 001; Shouyi Yin; Liang He 003 (INTERSPEECH, 2020)

GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent. - Yifan Yang; Zhaoshi Li; Yangdong Deng; Zhiwei Liu; Shouyi Yin; Shaojun Wei; Leibo Liu (ISCA, 2020)

CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. - Dibei Chen; Zhaoshi Li; Tianzhu Xiong; Zhiwei Liu; Jun Yang 006; Shouyi Yin; Shaojun Wei; Leibo Liu (MICRO, 2020)

TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks. - Huiyu Mo; Leibo Liu; Wenjing Hu; Wenping Zhu; Qiang Li 052; Ang Li; Shouyi Yin; Jian Chen; Xiaowei Jiang; Shaojun Wei (MICRO, 2020)

A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. - Leibo Liu; Jianfeng Zhu 001; Zhaoshi Li; Yanan Lu; Yangdong Deng; Jie Han 001; Shouyi Yin; Shaojun Wei (ACM Comput. Surv., 2020)

A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection. - Guiqiang Peng; Leibo Liu; Sheng Zhou 001; Shouyi Yin; Shaojun Wei (IEEE J. Solid State Circuits, 2020)

NTTU: An Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication. - Neng Zhang 002; Qiao Qin; Hang Yuan; Chenggao Zhou; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Computers, 2020)

Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform. - Zhendong Wang; Zihang Jiang; Zhen Wang 019; Xulong Tang; Cong Liu 005; Shouyi Yin; Yang Hu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Scheduling of Irregular Network Structures on CNN Accelerators. - Shixuan Zheng; Xianjue Zhang; Daoli Ou; Shibin Tang; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power. - Chenchen Deng; Bo Wang 023; Leibo Liu; Min Zhu 001; Youyu Wu; Hui Li; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 4K × 2K@60fps Multifunctional Video Display Processor for High Perceptual Image Quality. - Hang Wang; Xiang Li; Daqiang Han; Shiquan Yu; Shouyi Yin; Shaojun Wei; Nanning Zheng 001; Xuchong Zhang; Tiancheng Wang; Wenchang Li; Qiubo Chen; Pengju Ren; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT. - Neng Zhang 002; Bohan Yang 001; Chen Chen 083; Shouyi Yin; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020)

A Multi-Task Hardwired Accelerator for Face Detection and Alignment. - Huiyu Mo; Leibo Liu; Wenping Zhu; Qiang Li 052; Hong Liu; Shouyi Yin; Shaojun Wei (IEEE Trans. Circuits Syst. Video Technol., 2020)

Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation. - Leibo Liu; Xingchen Man; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2020)

Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings. - Liang Wang 020; Leibo Liu; Jie Han 001; Xiaohang Wang 001; Shouyi Yin; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2020)

Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based MMSE Detector for Massive MIMO Systems. - Leibo Liu; Guiqiang Peng; Pan Wang 003; Sheng Zhou 001; Qiushi Wei; Shouyi Yin; Shaojun Wei (IEEE Trans. Signal Process., 2020)

Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation. - Pan Wang 003; Leibo Liu; Sheng Zhou 001; Guiqiang Peng; Shouyi Yin; Shaojun Wei (IEEE Trans. Wirel. Commun., 2020)

LPE: Logarithm Posit Processing Element for Energy-Efficient Edge-Device Training. - Yang Wang 089; Dazheng Deng; Leibo Liu; Shaojun Wei; Shouyi Yin (AICAS, 2021)

HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning. - Yang Wang 089; Yubin Qin; Leibo Liu; Shaojun Wei; Shouyi Yin (AICAS, 2021)

Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs. - Cheng Li; Jiangyuan Gu; Shouyi Yin; Leibo Liu; Shaojun Wei (ASP-DAC, 2021)

A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating. - Song Zhang; Jiangyuan Gu; Shouyi Yin; Leibo Liu; Shaojun Wei (ASP-DAC, 2021)

GLMSnet: Single Channel Speech Separation Framework in Noisy and Reverberant Environments. - Huiyu Shi; Xi Chen; Tianlong Kong; Shouyi Yin; Peng Ouyang (ASRU, 2021)

Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU Encryption. - Zhendong Wang; Rujia Wang; Zihang Jiang; Xulong Tang; Shouyi Yin; Yang Hu 001 (ATS, 2021)

ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training. - Xinhan Lin; Liang Sun; Fengbin Tu; Leibo Liu; Xiangyu Li; Shaojun Wei; Shouyi Yin (DAC, 2021)

HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms. - Haichang Yang; Zhaoshi Li; Jiawei Wang; Shouyi Yin; Shaojun Wei; Leibo Liu (DATE, 2021)

FuseKNA: Fused Kernel Convolution based Accelerator for Deep Neural Networks. - Jianxun Yang; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Leibo Liu; Shaojun Wei; Shouyi Yin (HPCA, 2021)

Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs. - Dajiang Liu; Ting Liu; Xingyu Mo; Jiaxing Shang; Shouyi Yin (ICCAD, 2021)

Learnable Quantization Loss Function Based on Expectation. - Hao Sun; Yujuan Cheng; Yang Wang 089; Bin Wang; Shouyi Yin (ICAC, 2021)

Dynamic Multi-Scale Convolution for Dialect Identification. - Tianlong Kong; Shouyi Yin; Dawei Zhang; Wang Geng; Xin Wang; Dandan Song; Jinwen Huang; Huiyu Shi; Xiaorui Wang (Interspeech, 2021)

ABC-DIMM: Alleviating the Bottleneck of Communication in DIMM-based Near-Memory Processing with Inter-DIMM Broadcast. - Weiyi Sun; Zhaoshi Li; Shouyi Yin; Shaojun Wei; Leibo Liu (ISCA, 2021)

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. - Ruiqi Guo; Zhiheng Yue; Xin Si; Te Hu; Hao Li; Limei Tang; Yabing Wang; Leibo Liu; Meng-Fan Chang; Qiang Li 021; Shaojun Wei; Shouyi Yin (ISSCC, 2021)

9.2A 28nm 12.1TOPS/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. - Huiyu Mo; Wenping Zhu; Wenjing Hu; Guangbin Wang; Qiang Li 052; Ang Li; Shouyi Yin; Shaojun Wei; Leibo Liu (ISSCC, 2021)

A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation. - Ruiqi Guo; Hao Li; Ruhui Liu; Zhixiao Zhang; Limei Tang; Hao Sun; Leibo Liu; Meng-Fan Chang; Shaojun Wei; Shouyi Yin (VLSI Circuits, 2021)

A 28nm 276.55TFLOPS/W Sparse Deep-Neural-Network Training Processor with Implicit Redundancy Speculation and Batch Normalization Reformulation. - Yang Wang 089; Yubin Qin; Dazheng Deng; Jingchuan Wei; Tianbao Chen; Xinhan Lin; Leibo Liu; Shaojun Wei; Shouyi Yin (VLSI Circuits, 2021)

Fast substitution-box evaluation algorithm and its efficient masking scheme for block ciphers. - Hai Huang; Leibo Liu; Min Zhu 001; Shouyi Yin; Shaojun Wei (Sci. China Inf. Sci., 2021)

Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning. - Fengbin Tu; Weiwei Wu; Yang Wang 089; Hongjiang Chen; Feng Xiong; Man Shi; Ning Li; Jinyi Deng; Tianbao Chen; Leibo Liu; Shaojun Wei; Yuan Xie 001; et al. (IEEE J. Solid State Circuits, 2021)

Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning". - Fengbin Tu; Weiwei Wu; Yang Wang 089; Hongjiang Chen; Feng Xiong; Man Shi; Ning Li; Jinyi Deng; Tianbao Chen; Leibo Liu; Shaojun Wei; Yuan Xie 001; et al. (IEEE J. Solid State Circuits, 2021)

TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. - Jianxun Yang; Yuyao Kong; Zhao Zhang; Zhuangzhi Liu; Jing Zhou; Yiqi Wang 005; Yonggang Liu; Chenfu Guo; Te Hu; Congcong Li; Leibo Liu; Jin Zhang; et al. (IEEE J. Solid State Circuits, 2021)

Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters. - Jianfeng Zhu 001; Ao Luo; Guanhua Li; Bowei Zhang 002; Yong Wang; Gang Shan; Yi Li; Jianfeng Pan; Chenchen Deng; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2021)

A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs. - Yibo Wu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model. - Neng Zhang 002; Qiao Qin; Zongsheng Hou; Bohan Yang 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Flexible Rectification of a Speckle Projection System for Depth Sensing. - Kai Zhou; Shouyi Yin; Peng Ouyang; Yinan Liu; Shibin Tang (IEEE Trans. Instrum. Meas., 2021)

A 460 GOPS/W Improved Mnemonic Descent Method-Based Hardwired Accelerator for Face Alignment. - Huiyu Mo; Leibo Liu; Wenping Zhu; Qiang Li 052; Shouyi Yin; Shaojun Wei (IEEE Trans. Multim., 2021)

An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures. - Longlong Chen; Jianfeng Zhu 001; Yangdong Deng; Zhaoshi Li; Jian Chen; Xiaowei Jiang; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Parallel Distributed Syst., 2021)

Efficient access scheme for multi-bank based NTT architecture through conflict graph. - Xiangren Chen; Bohan Yang 001; Yong Lu; Shouyi Yin; Shaojun Wei; Leibo Liu (DAC, 2022)

Mixed-granularity parallel coarse-grained reconfigurable architecture. - Jinyi Deng; Linyun Zhang; Lei Wang; Jiawei Liu; Kexiang Deng; Shibin Tang; Jiangyuan Gu; Boxiao Han; Fei Xu; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2022)

MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation. - Zhiheng Yue; Yabing Wang; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2022)

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems. - Yibo Wu; Liang Wang 020; Xiaohang Wang 001; Jie Han 001; Jianfeng Zhu 001; Honglan Jiang; Shouyi Yin; Shaojun Wei; Leibo Liu (HPCA, 2022)

Atomic Dataflow based Graph-Level Workload Orchestration for Scalable DNN Accelerators. - Shixuan Zheng; Xianjue Zhang; Leibo Liu; Shaojun Wei; Shouyi Yin (HPCA, 2022)

A SHA-512 Hardware Implementation Based on Block RAM Storage Structure. - Mingyuan Yang; Yemeng Zhang; Bohan Yang 001; Hanning Wang; Shouyi Yin; Shaojun Wei; Leibo Liu (IPDPS Workshops, 2022)

CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process. - Xingchen Man; Jianfeng Zhu 001; Guihuan Song; Shouyi Yin; Shaojun Wei; Leibo Liu (ISCA, 2022)

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Ling Liang; Yufei Ding 001; Bongjin Kim; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (ISSCC, 2022)

A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Ling Liang; Liu Liu 017; Yufei Ding 001; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (ISSCC, 2022)

A 28nm 27.5TOPS/W Approximate-Computing-Based Transformer Processor with Asymptotic Sparsity Speculating and Out-of-Order Computing. - Yang Wang 089; Yubin Qin; Dazheng Deng; Jingchuan Wei; Yang Zhou; Yuanqi Fan; Tianbao Chen; Hao Sun; Leibo Liu; Shaojun Wei; Shouyi Yin (ISSCC, 2022)

A 28nm 48KOPS 3.4µJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems. - Yihong Zhu; Wenping Zhu; Min Zhu 001; Chongyang Li; Chenchen Deng; Chen Chen 083; Shuying Yin; Shouyi Yin; Shaojun Wei; Leibo Liu (ISSCC, 2022)

An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance. - Chenchen Deng; Min Zhu 001; Jinjiang Yang; Youyu Wu; Jiaji He; Bohan Yang 001; Jianfeng Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (Sci. China Inf. Sci., 2022)

FAQS: Communication-efficient Federate DNN Architecture and Quantization Co-Search for personalized Hardware-aware Preferences. - Hongjiang Chen; Yang Wang 089; Leibo Liu; Shaojun Wei; Shouyi Yin (CoRR, 2022)

HQNAS: Auto CNN deployment framework for joint quantization and architecture search. - Hongjiang Chen; Yang Wang 089; Leibo Liu; Shaojun Wei; Shouyi Yin (CoRR, 2022)

Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC). - Jung-Hwan Choi; Po-Chiun Huang; Shouyi Yin; Woogeun Rhee (IEEE J. Solid State Circuits, 2022)

A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction. - Huiyu Mo; Wenping Zhu; Wenjing Hu; Qiang Li 052; Ang Li; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2022)

Trainer: An Energy-Efficient Edge-Device Training Processor Supporting Dynamic Weight Pruning. - Yang Wang 089; Yubin Qin; Dazheng Deng; Jingchuan Wei; Tianbao Chen; Xinhan Lin; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE J. Solid State Circuits, 2022)

Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding. - Zongsheng Hou; Neng Zhang 002; Bohan Yang 001; Hanning Wang; Min Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

BitCluster: Fine-Grained Weight Quantization for Load-Balanced Bit-Serial Neural Network Accelerators. - Ang Li; Huiyu Mo; Wenping Zhu; Qiang Li 052; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA. - Baofen Yuan; Jianfeng Zhu 001; Xingchen Man; Zijiao Ma; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing. - Yang Wang 089; Dazheng Deng; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning. - Yang Wang 089; Yubin Qin; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation. - Yong Wu; Honglan Jiang; Zining Ma; Pengfei Gou; Yong Lu; Jie Han 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating. - Jianxun Yang; Fengbin Tu; Yixuan Li; Yiqi Wang 005; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

BR-CIM: An Efficient Binary Representation Computation-In-Memory Design. - Zhiheng Yue; Yabing Wang; Yubin Qin; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme. - Xiangren Chen; Bohan Yang 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium. - Cankun Zhao; Neng Zhang 002; Hanning Wang; Bohan Yang 001; Wenping Zhu; Zhengdong Li; Min Zhu 001; Shouyi Yin; Shaojun Wei; Leibo Liu (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions. - Xiaofeng Chen; Ruiqi Guo; Zhiheng Yue; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (AICAS, 2023)

TPE: A High-Performance Edge-Device Inference with Multi-level Transformational Mechanism. - Zhou Wang 005; Jingchuan Wei; Xiaonan Tang; Boxiao Han; Hongjun He; Leibo Liu; Shaojun Wei; Shouyi Yin (AICAS, 2023)

CIMFormer: A 38.9TOPS/W-8b Systolic CIM-Array Based Transformer Processor with Token-Slimmed Attention Reformulating and Principal Possibility Gathering. - Ruiqi Guo; Yang Wang 089; Xiaofeng Chen; Lei Wang; Hao Sun; Jingchuan Wei; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (A-SSCC, 2023)

A 28nm 49.7TOPS/W Sparse Transformer Processor with Random-Projection-Based Speculation, Multi-Stationary Dataflow, and Redundant Partial Product Elimination. - Yubin Qin; Yang Wang 089; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Yang Zhou; Yuanqi Fan; Jingchuan Wei; Tianbao Chen; Leibo Liu; Shaojun Wei; Yang Hu 001; et al. (A-SSCC, 2023)

DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs. - Dajiang Liu; Di Mou; Rong Zhu; Yan Zhuang; Jiaxing Shang; Jiang Zhong; Shouyi Yin (DAC, 2023)

CPE: An Energy-Efficient Edge-Device Training with Multi-dimensional Compression Mechanism. - Zhou Wang 005; Jingchuan Wei; Boxiao Han; Hongjun He; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2023)

RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. - Qidie Wu; Jiangyuan Gu; Youxu Lin; Boxiao Han; Hongjun He; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2023)

FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction. - Yubin Qin; Yang Wang 089; Dazheng Deng; Zhiren Zhao; Xiaolong Yang; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISCA, 2023)

MuITCIM: A 28nm $2.24 mu mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (ISSCC, 2023)

TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (ISSCC, 2023)

CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction. - Zhiheng Yue; Yang Wang 089; Huizheng Wang; Yabing Wang; Ruiqi Guo; Limei Tang; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2023)

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Boxiao Han; Hongjun He; Fengbin Tu; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (MICRO, 2023)

A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing. - Yang Wang 089; Yubin Qin; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2023)

Catch-Up Distillation: You Only Need to Train Once for Accelerating Sampling. - Shitong Shao; Xu Dai; Shouyi Yin; Lujun Li 001; Huanran Chen; Yang Hu 001 (CoRR, 2023)

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Fengbin Tu; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (CoRR, 2023)

WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow. - Haojia Hui; Jiangyuan Gu; Xunbo Hu; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (CoRR, 2023)

Wafer-scale Computing: Advancements, Challenges, and Future Perspectives. - Yang Hu 001; Xinhan Lin; Huizheng Wang; Zhen He; Xingmao Yu; Jiahao Zhang; Qize Yang; Zheng Xu; Sihan Guan; Jiahao Fang; Haoran Shang; Xinru Tang; et al. (CoRR, 2023)

TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Ling Liang; Liu Liu 017; Yufei Ding 001; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. - Fengbin Tu; Yiqi Wang 005; Zihan Wu 006; Ling Liang; Yufei Ding 001; Bongjin Kim; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention. - Yang Wang 089; Yubin Qin; Dazheng Deng; Jingchuan Wei; Yang Zhou; Yuanqi Fan; Tianbao Chen; Hao Sun; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE J. Solid State Circuits, 2023)

RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems. - Yihong Zhu; Wenping Zhu; Chongyang Li; Min Zhu 001; Chenchen Deng; Chen Chen 083; Shuying Yin; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE J. Solid State Circuits, 2023)

TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. - Mingyang Kou; Jiangyuan Gu; Hailong Yao; Shaojun Wei; Shouyi Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration. - Fengbin Tu; Yiqi Wang 005; Ling Liang; Yufei Ding 001; Leibo Liu; Shaojun Wei; Shouyi Yin; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition. - Weiwei Wu; Fengbin Tu; Mengqi Niu; Zhiheng Yue; Leibo Liu; Shaojun Wei; Xiangyu Li; Yang Hu 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. - Yiqi Wang 005; Fengbin Tu; Leibo Liu; Shaojun Wei; Yuan Xie 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. - Ruiqi Guo; Zhiheng Yue; Xin Si; Hao Li; Te Hu; Limei Tang; Yabing Wang; Hao Sun; Leibo Liu; Meng-Fan Chang; Qiang Li 021; Shaojun Wei; et al. (IEEE J. Solid State Circuits, 2023)

Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips. - Shaojun Wei; Xinhan Lin; Fengbin Tu; Yang Wang 089; Leibo Liu; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures. - Xiangyu Kong; Jianfeng Zhu 001; Xingchen Man; Guihuan Song; Yi Huang 036; Chenchen Deng; Pengfei Gou; Shouyi Yin; Shaojun Wei; Leibo Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

RTPE: A High Energy Efficiency Inference Processor with RISC-V based Transformation Mechanism. - Zhou Wang 005; Haochen Du; Baoyi Han; Yanqing Xu; Xiaonan Tang; Yang Zhou; Zhe Zheng; Wenpeng Cui; Yanwei Xiong; Shaojun Wei; Shushan Qiao; Shouyi Yin (AICAS, 2024)

RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism. - Zhou Wang 005; Haochen Du; Baoyi Han; Yanqing Xu; Xiaonan Tang; Yang Zhou; Zhe Zheng; Wenpeng Cui; Yanwei Xiong; Shaojun Wei; Shushan Qiao; Shouyi Yin (AICAS, 2024)

SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing. - Zhou Wang 005; Haochen Du; Jiuren Zhou; Yanqing Xu; Xiaonan Tang; Tianchun Ye 001; Shaojun Wei; Shushan Qiao; Shouyi Yin (APCCAS, 2024)

GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications. - Zhou Wang 005; Haochen Du; Jiuren Zhou; Yang Zhou; Xiaonan Tang; Tianchun Ye 001; Shaojun Wei; Shushan Qiao; Shouyi Yin (APCCAS, 2024)

A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Shaojun Wei; Yang Hu 001; Shouyi Yin (A-SSCC, 2024)

A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. - Pengyu He; Yuanzhe Zhao; Heng Xie; Yang Wang 089; Shouyi Yin; Li Li 064; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2024)

PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis. - Dajiang Liu; Decai Pan; Xiao Xiong; Jiaxing Shang; Shouyi Yin (DAC, 2024)

Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. - Xujiang Xiang; Zhiheng Yue; Yuxuan Li; Liuxin Lv; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference. - Zheng Xu; Xu Dai; Shaojun Wei; Shouyi Yin; Yang Hu 001 (DAC, 2024)

FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing. - Xiaolong Yang; Yang Wang 089; Yubin Qin; Jiachen Wang; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. - Zhiheng Yue; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping. - Dajiang Liu; Yuxin Xia; Jiaxing Shang; Jiang Zhong; Peng Ouyang; Shouyi Yin (HPCA, 2024)

A Lightweight 3D D2D Interface for Active Interposer Chiplet Systems. - Zheng Yang; Yafei Liu; Xiangyu Li; Shouyi Yin (ICTA, 2024)

MECLA: Memory-Compute-Efficient LLM Accelerator with Scaling Sub-matrix Partition. - Yubin Qin; Yang Wang 089; Zhiren Zhao; Xiaolong Yang; Yang Zhou; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISCA, 2024)

Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. - Zhiheng Yue; Huizheng Wang; Jiahao Fang; Jinyi Deng; Guangyang Lu; Fengbin Tu; Ruiqi Guo; Yuxuan Li; Yubin Qin; Yang Wang 089; Chao Li 009; Huiming Han; et al. (ISCA, 2024)

20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. - Ruiqi Guo; Lei Wang; Xiaofeng Chen; Hao Sun; Zhiheng Yue; Yubin Qin; Huiming Han; Yang Wang 089; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. - Zhiheng Yue; Xujiang Xiang; Fengbin Tu; Yang Wang 089; Yiming Wang; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. - Huizheng Wang; Jiahao Fang; Xinru Tang; Zhiheng Yue; Jinxi Li; Yubin Qin; Sihan Guan; Qinze Yang; Yang Wang 089; Chao Li 009; Yang Hu 001; Shouyi Yin (MICRO, 2024)

ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. - Yiqi Wang 005; Zhen He; Chenggang Zhao; Zihan Wu 006; Mingyu Gao 001; Huiming Han; Shaojun Wei; Yang Hu 001; Fengbin Tu; Shouyi Yin (VLSI Technology and Circuits, 2024)

A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation. - Ruiqi Guo; Xiaofeng Chen; Lei Wang; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication. - Yubin Qin; Yang Wang 089; Xiaolong Yang; Zhiren Zhao; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

Review of chiplet-based design: system architecture and interconnection. - Yafei Liu; Xiangyu Li; Shouyi Yin (Sci. China Inf. Sci., 2024)

SWG: an architecture for sparse weight gradient computation. - Weiwei Wu; Fengbin Tu; Xiangyu Li; Shaojun Wei; Shouyi Yin (Sci. China Inf. Sci., 2024)

Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture. - Jinyi Deng; Xinru Tang; Zhiheng Yue; Guangyang Lu; Qize Yang; Jiahao Zhang; Jinxi Li; Chao Li 009; Shaojun Wei; Yang Hu 001; Shouyi Yin (CoRR, 2024)

PALM: A Efficient Performance Simulator for Tiled Accelerators with Large-scale Model Training. - Jiahao Fang; Huizheng Wang; Qize Yang; Dehao Kong; Xu Dai; Jinyi Deng; Yang Hu 001; Shouyi Yin (CoRR, 2024)

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. - Huizheng Wang; Jiahao Fang; Xinru Tang; Zhiheng Yue; Jinxi Li; Yubin Qin; Sihan Guan; Qize Yang; Yang Wang 089; Chao Li 009; Yang Hu 001; Shouyi Yin (CoRR, 2024)

Tackling the Dynamicity in a Production LLM Serving System with SOTA Optimizations via Hybrid Prefill/Decode/Verify Scheduling on Efficient Meta-kernels. - Mingcong Song; Xinru Tang; Fengfan Hou; Jing Li; Wei Wei; Yipeng Ma; Runqiu Xiao; Hongjie Si; Dingcheng Jiang; Shouyi Yin; Yang Hu 001; Guoping Long (CoRR, 2024)

MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity. - Fengbin Tu; Zihan Wu 006; Yiqi Wang 005; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Shouyi Yin (IEEE J. Solid State Circuits, 2024)

CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering. - Ruiqi Guo; Xiaofeng Chen; Lei Wang; Yang Wang 089; Hao Sun; Jingchuan Wei; Huiming Han; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2024)

Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow. - Yubin Qin; Yang Wang 089; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Yang Zhou; Yuanqi Fan; Jingchuan Wei; Tianbao Chen; Leibo Liu; Shaojun Wei; Yang Hu 001; et al. (IEEE J. Solid State Circuits, 2024)

PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture. - Weiwei Wu; Fengbin Tu; Shaojun Wei; Xiangyu Li; Yang Hu 001; Shouyi Yin (ASAP, 2025)

DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures. - Haojia Hui; Jiangyuan Gu; Xunbo Hu; Shaojun Wei; Shouyi Yin (ASP-DAC, 2025)

Computing Efficiency Improvement for Multi-PEA CGRA with Built-in Control Design. - Jiangyuan Gu; Xunbo Hu; Zidi Qin; Shaojun Wei; Shouyi Yin (CF, 2025)

A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager. - Yuanzhe Zhao; Yang Wang 089; Yuheng Wang; Heng Xie; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Shouyi Yin; Minglei Zhang (CICC, 2025)

ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. - Zhen He; Yiqi Wang 005; Zihan Wu 006; Shaojun Wei; Yang Hu 001; Fengbin Tu; Shouyi Yin (HPCA, 2025)

WSC-LLM: Efficient LLM Service and Architecture Co-exploration for Wafer-scale Chips. - Zheng Xu; Dehao Kong; Jiaxin Liu; Jinxi Li; Jingxiang Hou; Xu Dai; Chao Li 009; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISCA, 2025)

PD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer. - Qize Yang; Taiquan Wei; Sihan Guan; Chengran Li; Haoran Shang; Jinyi Deng; Huizheng Wang; Chao Li 009; Lei Wang; Yan Zhang; Shouyi Yin; Yang Hu 001 (ISCA, 2025)

Cramming a Data Center into One Cabinet, a Co-Exploration of Computing and Hardware Architecture of Waferscale Chip. - Xingmao Yu; Dingcheng Jiang; Jinyi Deng; Jingyao Liu; Chao Li 009; Shouyi Yin; Yang Hu 001 (ISCA, 2025)

STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme. - Zhou Wang 005; Haochen Du; Vivek Mohan; Jiuren Zhou; Zhou Shu; Yanqing Xu; Baoyi Han; Xiaonan Tang; Shushan Qiao; Shouyi Yin; Anil A. Bharath; Emmanuel M. Drakakis (ISCAS, 2025)

GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism. - Zhou Wang 005; Haochen Du; Jiuren Zhou; Zhou Shu; Yanqing Xu; Vivek Mohan; Baoyi Han; Xiaonan Tang; Shushan Qiao; Shouyi Yin; Anil A. Bharath; Emmanuel M. Drakakis (ISCAS, 2025)

23.8 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensional Workflow Reformulation. - Yubin Qin; Yang Wang 089; Jiachen Wang; Zhiwei Lin; Yushu Zhao; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2025)

14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <-30 Loss for Compound AI. - Zhiheng Yue; Xujiang Xiang; Yang Wang 089; Ruiqi Guo; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2025)

A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array. - Ruiqi Guo; Zhiheng Yue; Yang Wang 089; Hao Li; Te Hu; Yabing Wang; Hao Sun; Jeng-Long Hsu; Yaojun Zhang; Bonan Yan; Leibo Liu; Ru Huang 001; et al. (IEEE J. Solid State Circuits, 2025)

Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design. - Jinyi Deng; Xinru Tang; Jiahao Zhang; Yuxuan Li; Linyun Zhang; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE Trans. Computers, 2025)

TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration. - Yiqi Wang 005; Zihan Wu 006; Weiwei Wu; Leibo Liu; Yang Hu 001; Shaojun Wei; Fengbin Tu; Shouyi Yin (IEEE J. Solid State Circuits, 2025)

CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction. - Zhiheng Yue; Yang Wang 089; Huizheng Wang; Ruiqi Guo; Fengbin Tu; Jianxun Yang; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2025)

BeaCIM: A Digital Compute-in-Memory DNN Processor With Bi-Directional Exponent Alignment for FP8 Training. - Yang Zhou; Yang Wang 089; Wenxin Yin; Yazheng Jiang; Jingchuan Wei; Yubin Qin; Yang Hu 001; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Chiplet Platform for Intelligent Radar/Sonar Leveraging Domain-Specific Reusable Active Interposer. - Yafei Liu; Dejian Li; Zheng Yang; Chaoqin Zhang; Yunlai Zhang; Xiangyu Li; Mingwei Cao; Shouyi Yin (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. - Xujiang Xiang; Zhiheng Yue; Xiaolong Zhang; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

HPCTransCompile: An AI Compiler Generated Dataset for High-Performance CUDA Transpilation and LLM Preliminary Exploration. - Jiaqi Lv; Xufeng He; Yanchen Liu; Xu Dai; Yang Hu 001; Shouyi Yin (CoRR, 2025)

An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2025)