Design space exploration for minimizing multi-project wafer production cost. - Rung-Bin Lin; Meng-Chiou Wu; Wei-Chiu Tseng; Ming-Hsine Kuo; Tsai-Ying Lin; Shr-Cheng Tsai (ASP-DAC, 2006)

Recognition of regular layout structures. - Yu-Cheng Chiang; Shr-Cheng Tsai; Rung-Bin Lin (ISQED, 2018)