Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. - Jean-Olivier Plouchart; Noah Zamdmer; Jonghae Kim; Melanie Sherony; Yue Tan; Asit Ray; Mohamed Talbi; Lawrence F. Wagner; Kun Wu; Naftali E. Lustig; Shreesh Narasimha; Patricia O'Neil; et al. (IBM J. Res. Dev., 2003)

Optimization of silicon technology for the IBM System z9. - Daniel J. Poindexter; Scott R. Stiffler; Philip T. Wu; Paul D. Agnello; Thomas Ivers; Shreesh Narasimha; Thomas B. Faure; Jed H. Rankin; David A. Grosch; Marc D. Knox; Daniel C. Edelstein; Mukesh Khare; et al. (IBM J. Res. Dev., 2007)

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications. - Subramanian S. Iyer; Greg G. Freeman; Colin Brodsky; Anthony I. Chou; Dan Corliss; Sameer H. Jain; Naftali E. Lustig; Vincent McGahay; Shreesh Narasimha; James P. Norum; Karen A. Nummy; Paul C. Parries; et al. (IBM J. Res. Dev., 2011)

Performance-optimized gate-first 22-nm SOI technology with embedded DRAM. - Gregory Freeman; Paul Chang; E. R. Engbrecht; K. J. Giewont; David F. Hilscher; M. Lagus; Timothy J. McArdle; B. Morgenfeld; Shreesh Narasimha; James P. Norum; K. A. Nummy; Paul C. Parries; et al. (IBM J. Res. Dev., 2015)

Breakdown data generation and in-die deconvolution methodology to address BEOL and MOL dielectric breakdown challenges. - Fen Chen; Carole Graas; Michael A. Shinosky; Kai Zhao; Shreesh Narasimha; Xiao Hu Liu; Chunyan Tian (Microelectron. Reliab., 2015)