Rough Neuron Based Neural Classifier. - Ashwin Kothari; Avinash G. Keskar; Rakesh Chalasani; Shreesha Srinath (ICETET, 2008)

Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. - Shreesha Srinath; Katherine Compton (FPGA, 2010)

Design and implementation of an "approximate" communication system for wireless media applications. - Sayandeep Sen; Syed Gilani; Shreesha Srinath; Stephen Schmitt; Suman Banerjee 001 (SIGCOMM, 2010)

Microarchitectural mechanisms to exploit value structure in SIMT architectures. - Ji Kim; Christopher Torng; Shreesha Srinath; Derek Lockhart; Christopher Batten (ISCA, 2013)

Design and Implementation of an "Approximate" Communication System for Wireless Media Applications. - Sayandeep Sen; Tan Zhang; Syed Gilani; Shreesha Srinath; Suman Banerjee 001; Sateesh Addepalli (IEEE/ACM Trans. Netw., 2013)

Architectural Specialization for Inter-Iteration Loop Dependence Patterns. - Shreesha Srinath; Berkin Ilbeyi; Mingxing Tan; Gai Liu; Zhiru Zhang; Christopher Batten (MICRO, 2014)

Improving high-level synthesis with decoupled data structure optimization. - Ritchie Zhao; Gai Liu; Shreesha Srinath; Christopher Batten; Zhiru Zhang (DAC, 2016)

Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. - Christopher Torng; Moyang Wang; Bharath Sudheendra; Nagaraj Murali; Suren Jayasuriya; Shreesha Srinath; Taylor Pritchard; Robin Ying; Christopher Batten (Hot Chips Symposium, 2016)

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. - Steve Dai; Ritchie Zhao; Gai Liu; Shreesha Srinath; Udit Gupta; Christopher Batten; Zhiru Zhang (FPGA, 2017)

Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs. - Ji Kim; Shunning Jiang; Christopher Torng; Moyang Wang; Shreesha Srinath; Berkin Ilbeyi; Khalid Al-Hawaj; Christopher Batten (MICRO, 2017)

A modular digital VLSI flow for high-productivity SoC design. - Brucek Khailany; Evgeni Khmer; Rangharajan Venkatesan; Jason Clemons; Joel S. Emer; Matthew Fojtik; Alicia Klinefelter; Michael Pellauer; Nathaniel Ross Pinckney; Yakun Sophia Shao; Shreesha Srinath; Christopher Torng; et al. (DAC, 2018)

An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware. - Tao Chen 045; Shreesha Srinath; Christopher Batten; G. Edward Suh (MICRO, 2018)

Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation. - Nursultan Kabylkas; Tommy Thorn; Shreesha Srinath; Polychronis Xekalakis; Jose Renau (MICRO, 2021)