SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. - Kevin Garello; Kevin Garello Yasin; S. Couet; Laurent Souriau; Johan Swerts; Sidharth Rao; Simon Van Beek; Wonsub Kim; Enlong Liu; Shreya Kundu; Diana Tsvetanova; Kris Croes; et al. (VLSI Circuits, 2018)

SOT-MRAM 300mm integration for low power and ultrafast embedded memories. - Kevin Garello; Farrukh Yasin; S. Couet; Laurent Souriau; Johan Swerts; Sidharth Rao; Simon Van Beek; Wonsub Kim; Enlong Liu; Shreya Kundu; Diana Tsvetanova; N. Jossart; et al. (CoRR, 2018)

STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. - Sidharth Rao; Woojin Kim; Simon Van Beek; Shreya Kundu; Manu Perumkunnil; Stefan Cosemans; Farrukh Yasin; Sebastien Couet; Robert Carpenter; Barry J. O'Sullivan; Shamin H. Sharifi; N. Jossart; et al. (IMW, 2021)

Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. - Simon Van Beek; Siddharth Rao; Shreya Kundu; Woojin Kim; Barry J. O'Sullivan; Stefan Cosemans; Farrukh Yasin; Robert Carpenter; Sebastien Couet; Shamin H. Sharifi; Nico Jossart; Davide Crotti; et al. (IRPS, 2021)

Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control. - S. Subhechha; Nouredine Rassoul; Attilio Belmonte; Hubert Hody; Harold Dekkers; Michiel J. van Setten; Adrian Vaisman Chasin; Shamin H. Sharifi; K. Banerjee; H. Puliyalil; Shreya Kundu; M. Pak; et al. (ICICDT, 2022)

First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP. - Gayle Murdoch; Matin O'Toole; Giulio Marti; Ankit Pokhrel; Diana Tsvetanova; Stefan Decoster; Shreya Kundu; Yusuke Oniki; Arame Thiam; Quoc Toan Le; Olalla Varela Pedreira; Alicja Lesniewska; et al. (VLSI Technology and Circuits, 2022)

Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode. - Taras Ravsher; Daniele Garbin; Andrea Fantini; Robin Degraeve; Sergiu Clima; Gabriele Luca Donadio; Shreya Kundu; Hubert Hody; Wouter Devulder; Jan Van Houdt; Valeri Afanas'ev; Romain Delhougne; et al. (VLSI Technology and Circuits, 2022)

Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm. - S. Subhechha; Nouredine Rassoul; Attilio Belmonte; Hubert Hody; Harold Dekkers; Michiel J. van Setten; Adrian Vaisman Chasin; Shamin H. Sharifi; S. Sutar; L. Magnarin; Umberto Celano; H. Puliyalil; et al. (VLSI Technology and Circuits, 2022)

Lowest IOFF < 3×10-21 A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT. - Attilio Belmonte; Shreya Kundu; S. Subhechha; Adrian Vaisman Chasin; Nouredine Rassoul; Harold Dekkers; H. Puliyalil; F. Seidel; P. Carolan; Romain Delhougne; Gouri Sankar Kar (VLSI Technology and Circuits, 2023)

Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer. - Souvik Ghosh 001; Quentin Smets; S. Banerjee; Tom Schram; Koen Kennes; R. Verheyen; P. Kumar; M.-E. Boulon; Benjamin Groven; H. M. Silva; Shreya Kundu; Daire Cott; et al. (VLSI Technology and Circuits, 2023)

Towards low damage and fab-compatible top-contacts in MX2 transistors using a combined synchronous pulse atomic layer etch and wet-chemical etch approach. - Shreya Kundu; D. H. van Doip; Tom Schram; Quentin Smets; S. Banerjee; Benjamin Groven; Daire Cott; Stefan Decoster; P. Bezard; F. Lazzarino; K. Banerjee; Souvik Ghosh 001; et al. (VLSI Technology and Circuits, 2023)

Comprehensive Performance and Reliability Assessment of Se-based Selector-Only Memory. - Taras Ravsher; Robin Degraeve; Daniele Garbin; Sergiu Clima; Andrea Fantini; Gabriele Luca Donadio; Shreya Kundu; Wouter Devulder; Hubert Hody; Goedele Potoms; Jan Van Houdt; Valeri Afanas'ev; et al. (IRPS, 2024)

Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects. - Anshul Gupta; Shreya Kundu; Stefan Decoster; K. Sah; G. Delie; B. Truijen; Davide Tierno; Giulio Marti; O. Varela Pedreira; B. Kenens; Y. Hermans; C. Adelmann; et al. (VLSI Technology and Circuits, 2024)

Accurate off-current evaluation by parasitic capacitance extraction in capacitor-less DRAM cells. - Daisuke Matsubayashi; Subhali Subhechha; Hyungrock Oh; Nouredine Rassoul; Shamin Houshmand Sharifi; Yiqun Wan; Shreya Kundu; Harinarayanan Puliyalil; Harold Dekkers; Alexandru Pavel; Inhee Lee 004; Gouri Sankar Kar; et al. (IMW, 2025)