Minimizing area and energy of deep learning hardware design using collective low precision and structured compression. - Shihui Yin; Gaurav Srivastava 001; Shreyas K. Venkataramanaiah; Chaitali Chakrabarti; Visar Berisha; Jae-sun Seo (ACSSC, 2017)

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. - Shihui Yin; Shreyas K. Venkataramanaiah; Gregory K. Chen; Ram Krishnamurthy 001; Yu Cao 001; Chaitali Chakrabarti; Jae-sun Seo (BioCAS, 2017)

Automatic Compiler Based FPGA Accelerator for CNN Training. - Shreyas Kolala Venkataramanaiah; Yufei Ma 002; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-sun Seo (FPL, 2019)

FixyNN: Energy-Efficient Real-Time Mobile Computer Vision Hardware Acceleration via Transfer Learning. - Paul N. Whatmough; Chuteng Zhou; Patrick Hansen; Shreyas K. Venkataramanaiah; Jae-sun Seo; Matthew Mattina (SysML, 2019)

FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning. - Paul N. Whatmough; Chuteng Zhou; Patrick Hansen; Shreyas K. Venkataramanaiah; Jae-sun Seo; Matthew Mattina (CoRR, 2019)

FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. - Shreyas K. Venkataramanaiah; Han-Sok Suh; Shihui Yin; Eriko Nurvitadhi; Aravind Dasu; Yu Cao 001; Jae-Sun Seo (ICCAD, 2020)

Efficient and Modularized Training on FPGA for Real-time Applications. - Shreyas Kolala Venkataramanaiah; Xiaocong Du; Zheng Li 020; Shihui Yin; Yu Cao 001; Jae-sun Seo (IJCAI, 2020)

Online Knowledge Acquisition with the Selective Inherited Model. - Xiaocong Du; Shreyas Kolala Venkataramanaiah; Zheng Li 020; Jae-sun Seo; Frank Liu 001; Yu Cao 001 (IJCNN, 2020)

Deep Neural Network Training Accelerator Designs in ASIC and FPGA. - Shreyas K. Venkataramanaiah; Shihui Yin; Yu Cao 001; Jae-Sun Seo (ISOCC, 2020)

FixyFPGA: Efficient FPGA Accelerator for Deep Neural Networks with High Element-Wise Sparsity and without External Memory Access. - Jian Meng; Shreyas Kolala Venkataramanaiah; Chuteng Zhou; Patrick Hansen; Paul N. Whatmough; Jae-sun Seo (FPL, 2021)

Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA. - Han-Sok Suh; Jian Meng; Ty Nguyen; Shreyas K. Venkataramanaiah; Vijay Kumar 001; Yu Cao 001; Jae-sun Seo (FPT, 2021)

A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. - Shreyas Kolala Venkataramanaiah; Jian Meng; Han-Sok Suh; Injune Yeo; Jyotishman Saikia; Sai Kiran Cherupally; Yichi Zhang 006; Zhiru Zhang; Jae-sun Seo (ESSCIRC, 2022)

Efficient continual learning at the edge with progressive segmented training. - Xiaocong Du; Shreyas Kolala Venkataramanaiah; Zheng Li 020; Han-Sok Suh; Shihui Yin; Gokul Krishnan; Frank Liu 001; Jae-sun Seo; Yu Cao 001 (Neuromorph. Comput. Eng., 2022)

FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro. - Jyotishman Saikia; Amitesh Sridharan; Injune Yeo; Shreyas K. Venkataramanaiah; Deliang Fan; Jae-Sun Seo (ESSCIRC, 2023)

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. - Shreyas Kolala Venkataramanaiah; Jian Meng; Han-Sok Suh; Injune Yeo; Jyotishman Saikia; Sai Kiran Cherupally; Yichi Zhang 006; Zhiru Zhang; Jae-Sun Seo (IEEE J. Solid State Circuits, 2023)