Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. - Shrirang K. Karandikar; Sachin S. Sapatnekar (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Logical effort based technology mapping. - Shrirang K. Karandikar; Sachin S. Sapatnekar (ICCAD, 2004)

Fast estimation of area-delay trade-offs in circuit sizing. - Shrirang K. Karandikar; Sachin S. Sapatnekar (ISCAS (4), 2005)

Fast comparisons of circuit implementations. - Shrirang K. Karandikar; Sachin S. Sapatnekar (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Fast Electrical Correction Using Resizing and Buffering. - Shrirang K. Karandikar; Charles J. Alpert; Mehmet Can Yildiz; Paul Villarrubia; Stephen T. Quay; T. Mahmud (ASP-DAC, 2007)

The nuts and bolts of physical synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (SLIP, 2007)

Techniques for Fast Physical Synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (Proc. IEEE, 2007)

Fast Algorithms for Slew-Constrained Minimum Cost Buffering. - Shiyan Hu 001; Charles J. Alpert; Jiang Hu; Shrirang K. Karandikar; Zhuo Li 001; Weiping Shi; Chin Ngai Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. - Shrirang K. Karandikar; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

FIRA - a novel method for benchmarking the cache hierarchy. - Varad R. Deshmukh; Nishchay S. Mhatre; Shrirang K. Karandikar (COMPUTE, 2012)